Received: by 2002:a05:6a10:6744:0:0:0:0 with SMTP id w4csp2621572pxu; Sat, 10 Oct 2020 01:39:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxDbNu1jKJBv1hX49UO0R+lMHlqVSQwM00eqQ4Im2a/nX2YEBiYtSAi0O4LJNV5zUYWU13C X-Received: by 2002:a17:906:7857:: with SMTP id p23mr18389449ejm.61.1602319145223; Sat, 10 Oct 2020 01:39:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1602319145; cv=none; d=google.com; s=arc-20160816; b=emv+Qv4RZoJW9cPbJ6Imhh63MKoHF0lEOLawYuDITvuoVnAFQBBx12tq3UDZOHlB// QanOyRHWqXyl4uALHRxM76eKSX4WUgFrdJCLaBSjDtkooaZRm+VHP7KeG8Fm6rrLr5eV 5LmVfe7IzCcpAlCMtbpJfGBfASf8rUlaFtbN9KMNHFKwg80Bz1l/3Ici3ZG9jEBzK+Gf db4pKLcnzu+MgrXO4elxwfaOt2IsONBiRcLjXeNrdQd7e1P2cygKVQiNm4p2evNUOnw5 x+8tkTtq3nhm7OyheSsTqgjRcxdjUetLS9KCzFs3GJdB4AoB2cdNWy8Q52ywmwo5swoz XAfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:message-id:date:subject:cc:to:from; bh=iarkbxwLbWtQu/pVCZuDRnpB6ap26xUmEvPMSyC17ZM=; b=Iw9BGgFm2EYy019te56Cm5bqMyJZrHuDactH2CGmXj7tTxdF21XiMEIzPTwwdDrSOe 2qymQSKZJXONscjZK19nDjf+pfHBzhQpqYBjed27l2Hlh7WrxswLHQtAS1c0P1F+IHsd XfD1QBJuiaVtTnjaWGNT2/SAUjNgw8T4uZOnaq1qpS6HgqxXmY1h2THBBRepz4wJPqs5 BL2xf4C1U642bqYGeczjp7s/XeFuYcb09gOeap0q/Wd9w0gHDTfnBqFL7eYQAny/ObEb AQvLHo93cdnM8zop4Endi9ObgvmV0PH2fY6NblQWbcqnW3EK3f3cv+NY/PHmwB2OmUnw 69/A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id l25si7706841eje.688.2020.10.10.01.38.41; Sat, 10 Oct 2020 01:39:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730536AbgJJFed (ORCPT + 99 others); Sat, 10 Oct 2020 01:34:33 -0400 Received: from alexa-out.qualcomm.com ([129.46.98.28]:18434 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730349AbgJJFcN (ORCPT ); Sat, 10 Oct 2020 01:32:13 -0400 Received: from ironmsg07-lv.qualcomm.com (HELO ironmsg07-lv.qulacomm.com) ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 09 Oct 2020 22:32:08 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg07-lv.qulacomm.com with ESMTP/TLS/AES256-SHA; 09 Oct 2020 22:32:06 -0700 X-QCInternal: smtphost Received: from mdalam-linux.qualcomm.com ([10.201.2.71]) by ironmsg02-blr.qualcomm.com with ESMTP; 10 Oct 2020 11:01:44 +0530 Received: by mdalam-linux.qualcomm.com (Postfix, from userid 466583) id B9926217BA; Sat, 10 Oct 2020 11:01:42 +0530 (IST) From: Md Sadre Alam To: agross@kernel.org, bjorn.andersson@linaro.org, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, robh+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: mdalam@codeaurora.org, sricharan@codeaurora.org Subject: [PATCH 0/5] mtd: rawnand: qcom: Add support for QSPI nand Date: Sat, 10 Oct 2020 11:01:37 +0530 Message-Id: <1602307902-16761-1-git-send-email-mdalam@codeaurora.org> X-Mailer: git-send-email 2.7.4 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org QPIC 2.0 supports Serial NAND support in addition to all features and commands in QPIC 1.0 for parallel NAND. Parallel and Serial NAND cannot operate simultaneously. QSPI nand devices will connect to QPIC IO_MACRO block of QPIC controller. There is a separate IO_MACRO clock for IO_MACRO block. Default IO_MACRO block divide the input clock by 4. so if IO_MACRO input clock is 320MHz then on bus it will be 80MHz, so QSPI nand device should also support this frequency. QPIC provides 4 data pins to QSPI nand. In standard SPI mode (x1 mode) data transfer will occur on only 2 pins one pin for Serial data in and one for serial data out. In QUAD SPI mode (x4 mode) data transfer will occur at all the four data lines. QPIC controller supports command for x1 mode and x4 mode. Md Sadre Alam (5): dt-bindings: qcom_nandc: IPQ5018 QPIC NAND documentation mtd: rawnand: qcom: Add initial support for qspi nand mtd: rawnand: qcom: Read QPIC version mtd: rawnand: qcom: Enable support for erase,read & write for serial nand. mtd: rawnand: qcom: Add support for serial training. .../devicetree/bindings/mtd/qcom_nandc.txt | 3 + drivers/mtd/nand/raw/nand_ids.c | 13 + drivers/mtd/nand/raw/qcom_nandc.c | 502 ++++++++++++++++++++- 3 files changed, 494 insertions(+), 24 deletions(-) -- 2.7.4