Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
From:   Ran Wang <ran.wang_1@nxp.com>
To:     Rob Herring <robh+dt@kernel.org>
CC:     "linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Biwen Li <biwen.li@nxp.com>, Ran Wang <ran.wang_1@nxp.com>,
        Leo Li <leoyang.li@nxp.com>, Shawn Guo <shawnguo@kernel.org>
Subject: RE: [PATCH v3 1/5] Documentation: dt: binding: fsl: Add
 'fsl,ippdexpcr1-alt-reg' property
Thread-Topic: [PATCH v3 1/5] Documentation: dt: binding: fsl: Add
 'fsl,ippdexpcr1-alt-reg' property
Thread-Index: AQHWljrqSTvZaBY98UGNWSX3I/ZV+KmQJBKA
Date:   Sat, 10 Oct 2020 01:57:00 +0000
Message-ID: <AM6PR04MB54130FE1CC9B6A4C8DF2D538F1090@AM6PR04MB5413.eurprd04.prod.outlook.com>
References: <20200929082234.36619-1-ran.wang_1@nxp.com>
In-Reply-To: <20200929082234.36619-1-ran.wang_1@nxp.com>
Accept-Language: en-US
Content-Language: en-US
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-MS-Exchange-CrossTenant-Network-Message-Id: 4ffc9f5f-7d72-4258-fb8d-08d86cbfc705
X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Oct 2020 01:57:00.5717
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-CrossTenant-userprincipalname: 0UnVgVCXoVdaJe+62QQYjbklA8r57LwLb2tKvpsxcW981SjHZg50IyaPYmSjMo+o7tOKyyF96lN/jR5zIwf6Uw==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB4965
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

Hi Rob,

On Tuesday, September 29, 2020 4:23 PM, Ran Wang wrote:
>=20
> From: Biwen Li <biwen.li@nxp.com>
>=20
> The 'fsl,ippdexpcr1-alt-reg' property is used to handle an errata A-00864=
6 on
> LS1021A.
>=20
> Signed-off-by: Biwen Li <biwen.li@nxp.com>
> Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
> ---
> Change in v3:
>  - Simplize related proterty definition and rename it.

Could you please comment for this version? Thanks in advance.

Regards,
Ran

> Change in v2:
>  - None
>=20
>  Documentation/devicetree/bindings/soc/fsl/rcpm.txt | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>=20
> diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> index 5a33619..62a22fc 100644
> --- a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> +++ b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> @@ -34,6 +34,9 @@ Chassis Version		Example Chips
>  Optional properties:
>   - little-endian : RCPM register block is Little Endian. Without it RCPM
>     will be Big Endian (default case).
> + - fsl,ippdexpcr1-alt-reg : The property is trying to workaround a
> +   hardware issue (found on SoC LS1021A only), if pressent, RCPM driver
> +   will use SCFG_SPARECR8 as a shadow register for RCPM_IPPDEXPCR1.
>=20
>  Example:
>  The RCPM node for T4240:
> @@ -43,6 +46,15 @@ The RCPM node for T4240:
>  		#fsl,rcpm-wakeup-cells =3D <2>;
>  	};
>=20
> +The RCPM node for LS1021A:
> +	rcpm: rcpm@1ee2140 {
> +		compatible =3D "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+";
> +		reg =3D <0x0 0x1ee2140 0x0 0x8>;
> +		#fsl,rcpm-wakeup-cells =3D <2>;
> +		fsl,ippdexpcr1-alt-reg;
> +	};
> +
> +
>  * Freescale RCPM Wakeup Source Device Tree Bindings
>  -------------------------------------------
>  Required fsl,rcpm-wakeup property should be added to a device node if th=
e
> device
> --
> 2.7.4