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Date:   Wed, 14 Oct 2020 14:58:46 +0200
From:   Miquel Raynal <miquel.raynal@bootlin.com>
To:     Fabio Estevam <festevam@gmail.com>
Cc:     Florian Fainelli <f.fainelli@gmail.com>,
        Jim Quinlan <james.quinlan@broadcom.com>,
        Stephen Rothwell <sfr@canb.auug.org.au>,
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        Naresh Kamboju <naresh.kamboju@linaro.org>,
        Joerg Roedel <joro@8bytes.org>,
        Robin Murphy <robin.murphy@arm.com>,
        Poonam Aggrwal <poonam.aggrwal@nxp.com>,
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        masonccyang@mxic.com.tw, Will Deacon <will@kernel.org>,
        "Z.Q. Hou" <Zhiqiang.Hou@nxp.com>, Christoph Hellwig <hch@lst.de>
Subject: Re: arm-smmu 5000000.iommu: Cannot accommodate DMA offset for IOMMU
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Hello,

Fabio Estevam <festevam@gmail.com> wrote on Wed, 14 Oct 2020 09:28:49
-0300:

> Hi Florian,
> 
> On Sun, Oct 11, 2020 at 6:59 PM Florian Fainelli <f.fainelli@gmail.com> wrote:
> 
> > however the NAND warning still remains. Someone else familiar with these
> > NXP development boards should fix the DTS so as to provide the require
> > ECC strength property.  
> 
> The ECC NAND warning looks like a regression.
> 
> I had originally reported it for an imx27 board and now I also pointed
> out that it also affects Layerscape:
> https://lore.kernel.org/linux-mtd/20201013193652.0c535c7c@xps13/T/#m09fad7eacdf86aee0834bbd8863d6d5ee2e69f8c

I think this thread initially reported two distinct defects, one has
been solved, the second one is in my hands but I couldn't find the root
cause yet. I tried to reproduce, without luck, with another NAND
controller. If someone has an imx based board and a NAND controller on
it, I would appreciate some help.

Thanks,
Miquèl