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From:   Fabien Parent <fparent@baylibre.com>
Date:   Wed, 14 Oct 2020 18:25:33 +0200
Message-ID: <CAOwMV_wskn9RiWsX44xL8CFTX-3coS9+bXaJxK8y4eBBOr0z_Q@mail.gmail.com>
Subject: Re: [PATCH v2 2/2] drm/mediatek: mtk_hdmi: add MT8167 support for HDMI
To:     Chun-Kuang Hu <chunkuang.hu@kernel.org>
Cc:     linux-kernel <linux-kernel@vger.kernel.org>,
        "moderated list:ARM/Mediatek SoC support" 
        <linux-mediatek@lists.infradead.org>,
        Linux ARM <linux-arm-kernel@lists.infradead.org>,
        DRI Development <dri-devel@lists.freedesktop.org>,
        Matthias Brugger <matthias.bgg@gmail.com>,
        Daniel Vetter <daniel@ffwll.ch>,
        David Airlie <airlied@linux.ie>,
        Philipp Zabel <p.zabel@pengutronix.de>
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Hi Chun-Kuang,

On Wed, Oct 14, 2020 at 3:00 PM Chun-Kuang Hu <chunkuang.hu@kernel.org> wro=
te:
>
> Hi, Fabien:
>
> Fabien Parent <fparent@baylibre.com> =E6=96=BC 2020=E5=B9=B410=E6=9C=8814=
=E6=97=A5 =E9=80=B1=E4=B8=89 =E4=B8=8A=E5=8D=882:19=E5=AF=AB=E9=81=93=EF=BC=
=9A
> >
> > Add support for HDMI on MT8167. HDMI on MT8167 is similar to
> > MT8173/MT2701 execpt for the two registers: SYS_CFG1C and SYS_CFG20
>
> I think you should drop this series. According to Mediatek HDMI
> binding document [1], the second parameter of mediatek,syscon-hdmi is
> the register offset. I think you could set register offset to 0x800
> for mt8167.
Ok, thank you. I will try it.

>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tr=
ee/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt?h=
=3Dv5.9
>
> Regards,
> Chun-Kuang.
>
> >
> > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> > ---
> >
> > Changelog:
> > v2: fix name of pdata structure
> >
> >  drivers/gpu/drm/mediatek/mtk_hdmi.c      | 7 +++++++
> >  drivers/gpu/drm/mediatek/mtk_hdmi_regs.h | 2 ++
> >  2 files changed, 9 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/medi=
atek/mtk_hdmi.c
> > index 57370c036497..484ea9cd654a 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> > @@ -1835,9 +1835,16 @@ static struct mtk_hdmi_data mt8173_hdmi_driver_d=
ata =3D {
> >         .sys_cfg20 =3D HDMI_SYS_CFG20,
> >  };
> >
> > +static struct mtk_hdmi_data mt8167_hdmi_driver_data =3D {
> > +       .sys_cfg1c =3D MT8167_HDMI_SYS_CFG1C,
> > +       .sys_cfg20 =3D MT8167_HDMI_SYS_CFG20,
> > +};
> > +
> >  static const struct of_device_id mtk_drm_hdmi_of_ids[] =3D {
> >         { .compatible =3D "mediatek,mt8173-hdmi",
> >           .data =3D &mt8173_hdmi_driver_data },
> > +       { .compatible =3D "mediatek,mt8167-hdmi",
> > +         .data =3D &mt8167_hdmi_driver_data },
> >         {}
> >  };
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h b/drivers/gpu/drm=
/mediatek/mtk_hdmi_regs.h
> > index 2050ba45b23a..a0f9c367d7aa 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
> > @@ -195,6 +195,7 @@
> >  #define GEN_RGB                                (0 << 7)
> >
> >  #define HDMI_SYS_CFG1C         0x000
> > +#define MT8167_HDMI_SYS_CFG1C  0x800
> >  #define HDMI_ON                                BIT(0)
> >  #define HDMI_RST                       BIT(1)
> >  #define ANLG_ON                                BIT(2)
> > @@ -211,6 +212,7 @@
> >  #define HTPLG_PIN_SEL_OFF              BIT(30)
> >  #define AES_EFUSE_ENABLE               BIT(31)
> >  #define HDMI_SYS_CFG20         0x004
> > +#define MT8167_HDMI_SYS_CFG20  0x804
> >  #define DEEP_COLOR_MODE_MASK           (3 << 1)
> >  #define COLOR_8BIT_MODE                        (0 << 1)
> >  #define COLOR_10BIT_MODE               (1 << 1)
> > --
> > 2.28.0
> >