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[71.174.203.64]) by smtp.gmail.com with ESMTPSA id d21sm315020ioi.39.2020.10.14.11.38.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 14 Oct 2020 11:38:21 -0700 (PDT) Subject: Re: [PATCH v1 0/8] perf c2c: Refine the organization of metrics To: Leo Yan , Arnaldo Carvalho de Melo , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Andi Kleen , David Ahern , Don Zickus , Al Grant , James Clark , linux-kernel@vger.kernel.org References: <20201014050921.5591-1-leo.yan@linaro.org> From: Joe Mario Message-ID: <79f2db37-a03f-c01f-0b3b-4e2d3ed429f4@redhat.com> Date: Wed, 14 Oct 2020 14:38:19 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: <20201014050921.5591-1-leo.yan@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/14/20 1:09 AM, Leo Yan wrote: > This patch set is to refine metrics output organization. > > If we reivew the current memory metrics in Perf c2c tool, it doesn't > orgnize the metrics with directive approach; thus user needs to take > time to dig into every statistics item. On the other hand, if use the > "summary and breakdown" approach, the output result will be easier for > reviewing by users, e.g. the output result can firstly give out the > summary values, and then the later items will breakdown into more > detailed statistics. > > For this reason, this patch is to reorgnize the metrics and it only > changes for the "Shared Data Cache Line Table": it firstly displays the > summary values for total records, total loads, total stores; then it > breaks these summary values into small values, with the order from the > most near memory node ("CPU Load Hit") to more far nodes > ("LLC Load Hit", "RMT Load Hit", "Load Dram"). > > "LLC Load Hit" = "LclHit" + "LclHitm" > > "RMT Load Hit" = "RmtHit" + "RmtHitm" \ > -> LLC Load Miss > "Load Dram" = "Lcl" + "Rmt" / > > Another main reason for this patch set is wanting to extend "perf c2c" > to support Arm SPE memory event, but Arm SPE doesn't contain 'HTIM' tag > in its default trace data, for this case if want to analyze cache false > sharing issue, we need to rely on LLC metrics + multi-threading info. > So this patch set can be friendly to show LLC related metrics in the > "Shared Data Cache Line Table"; for sorting cache lines with LLC metrics > which will be sent out with another separate patch set. > > > > Leo Yan (8): > perf c2c: Display the total numbers continuously > perf c2c: Display "Total Stores" as a standalone metrics > perf c2c: Organize metrics based on memory hierarchy > perf c2c: Change header from "LLC Load Hitm" to "Load Hitm" > perf c2c: Use more explicit headers for HITM > perf c2c: Change header for LLC local hit > perf c2c: Correct LLC load hit metrics > perf c2c: Add metrics "RMT Load Hit" > > tools/perf/builtin-c2c.c | 83 +++++++++------------------------------- > 1 file changed, 18 insertions(+), 65 deletions(-) Hi Leo: I ran your patches through some perf c2c tests and it all looks good. I agree the new format of the "Shared Data Cache Line Table" makes more sense now. And it still holds together nicely when sorted on local HitMs (-d lcl). Thank you for doing this. Joe Tested-by: Joe Mario