Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
From:   Min Li <min.li.xe@renesas.com>
To:     Min Li <min.li.xe@renesas.com>,
        "richardcochran@gmail.com" <richardcochran@gmail.com>
CC:     "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH net 4/4] ptp: ptp_idt82p33: support individually configure
 output by index
Thread-Topic: [PATCH net 4/4] ptp: ptp_idt82p33: support individually
 configure output by index
Thread-Index: AQHWbNOrfUA0C0DGnkCUtI/kv55TQ6mZebwQ
Date:   Thu, 15 Oct 2020 19:30:57 +0000
Message-ID: <OSAPR01MB178051B4AC87B84D2A4B18FFBA020@OSAPR01MB1780.jpnprd01.prod.outlook.com>
References: <1596815903-11144-1-git-send-email-min.li.xe@renesas.com>
In-Reply-To: <1596815903-11144-1-git-send-email-min.li.xe@renesas.com>
Accept-Language: en-CA, en-US
Content-Language: en-US
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-MS-Exchange-CrossTenant-Network-Message-Id: 5c8cab35-cfad-426b-d685-08d87140d736
X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Oct 2020 19:30:57.3397
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 53d82571-da19-47e4-9cb4-625a166a4a2a
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-CrossTenant-userprincipalname: 7ngGrjcm2uc5iBjSRgQoT/268OIqCiKbacAANf5LC1zvKtwYY+CMOmoB5hrmhI2xWL6Co9LW+vvPWfvVMvVyqA==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: OSBPR01MB2583
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

Hi David/Richard

When you have time, can you take a look at this change? Thanks

Min

-----Original Message-----
From: min.li.xe@renesas.com <min.li.xe@renesas.com>=20
Sent: August 7, 2020 11:58 AM
To: richardcochran@gmail.com
Cc: netdev@vger.kernel.org; linux-kernel@vger.kernel.org; Min Li <min.li.xe=
@renesas.com>
Subject: [PATCH net 4/4] ptp: ptp_idt82p33: support individually configure =
output by index

From: Min Li <min.li.xe@renesas.com>

Enable/disable individual output by index instead of by output_mask

Signed-off-by: Min Li <min.li.xe@renesas.com>
---
 drivers/ptp/ptp_idt82p33.c | 62 ++++++++++++++++++++++++++++++++++--------=
----
 drivers/ptp/ptp_idt82p33.h |  2 ++
 2 files changed, 48 insertions(+), 16 deletions(-)

diff --git a/drivers/ptp/ptp_idt82p33.c b/drivers/ptp/ptp_idt82p33.c index =
2d62aed..b3c82d7 100644
--- a/drivers/ptp/ptp_idt82p33.c
+++ b/drivers/ptp/ptp_idt82p33.c
@@ -578,33 +578,46 @@ static long idt82p33_sync_tod_work_handler(struct ptp=
_clock_info *ptp)
 	return ret;
 }
=20
-static int idt82p33_pps_enable(struct idt82p33_channel *channel, bool enab=
le)
+static int idt82p33_output_enable(struct idt82p33_channel *channel,
+				  bool enable, unsigned int outn)
 {
 	struct idt82p33 *idt82p33 =3D channel->idt82p33;
-	u8 mask, outn, val;
 	int err;
+	u8 val;
+
+	err =3D idt82p33_read(idt82p33, OUT_MUX_CNFG(outn), &val, sizeof(val));
+
+	if (err)
+		return err;
+
+	if (enable)
+		val &=3D ~SQUELCH_ENABLE;
+	else
+		val |=3D SQUELCH_ENABLE;
+
+	return idt82p33_write(idt82p33, OUT_MUX_CNFG(outn), &val,=20
+sizeof(val)); }
+
+static int idt82p33_output_mask_enable(struct idt82p33_channel *channel,
+				       bool enable)
+{
+	u16 mask;
+	int err;
+	u8 outn;
=20
 	mask =3D channel->output_mask;
 	outn =3D 0;
=20
 	while (mask) {
-		if (mask & 0x1) {
-			err =3D idt82p33_read(idt82p33, OUT_MUX_CNFG(outn),
-					    &val, sizeof(val));
-			if (err)
-				return err;
=20
-			if (enable)
-				val &=3D ~SQUELCH_ENABLE;
-			else
-				val |=3D SQUELCH_ENABLE;
+		if (mask & 0x1) {
=20
-			err =3D idt82p33_write(idt82p33, OUT_MUX_CNFG(outn),
-					     &val, sizeof(val));
+			err =3D idt82p33_output_enable(channel, enable, outn);
=20
 			if (err)
 				return err;
 		}
+
 		mask >>=3D 0x1;
 		outn++;
 	}
@@ -612,6 +625,20 @@ static int idt82p33_pps_enable(struct idt82p33_channel=
 *channel, bool enable)
 	return 0;
 }
=20
+static int idt82p33_perout_enable(struct idt82p33_channel *channel,
+				  bool enable,
+				  struct ptp_perout_request *perout) {
+	unsigned int flags =3D perout->flags;
+
+	/* Enable/disable output based on output_mask */
+	if (flags =3D=3D PEROUT_ENABLE_OUTPUT_MASK)
+		return idt82p33_output_mask_enable(channel, enable);
+
+	/* Enable/disable individual output instead */
+	return idt82p33_output_enable(channel, enable, perout->index); }
+
 static int idt82p33_enable_tod(struct idt82p33_channel *channel)  {
 	struct idt82p33 *idt82p33 =3D channel->idt82p33; @@ -625,7 +652,8 @@ stat=
ic int idt82p33_enable_tod(struct idt82p33_channel *channel)
 	if (err)
 		return err;
=20
-	err =3D idt82p33_pps_enable(channel, false);
+	if (0)
+		err =3D idt82p33_output_mask_enable(channel, false);
=20
 	if (err) {
 		dev_err(&idt82p33->client->dev,
@@ -681,14 +709,16 @@ static int idt82p33_enable(struct ptp_clock_info *ptp=
,
=20
 	if (rq->type =3D=3D PTP_CLK_REQ_PEROUT) {
 		if (!on)
-			err =3D idt82p33_pps_enable(channel, false);
+			err =3D idt82p33_perout_enable(channel, false,
+						     &rq->perout);
=20
 		/* Only accept a 1-PPS aligned to the second. */
 		else if (rq->perout.start.nsec || rq->perout.period.sec !=3D 1 ||
 		    rq->perout.period.nsec) {
 			err =3D -ERANGE;
 		} else
-			err =3D idt82p33_pps_enable(channel, true);
+			err =3D idt82p33_perout_enable(channel, true,
+						     &rq->perout);
 	}
=20
 	mutex_unlock(&idt82p33->reg_lock);
diff --git a/drivers/ptp/ptp_idt82p33.h b/drivers/ptp/ptp_idt82p33.h index =
1dcd2c0..5008998 100644
--- a/drivers/ptp/ptp_idt82p33.h
+++ b/drivers/ptp/ptp_idt82p33.h
@@ -56,6 +56,8 @@
 #define PLL_MODE_SHIFT                    (0)
 #define PLL_MODE_MASK                     (0x1F)
=20
+#define PEROUT_ENABLE_OUTPUT_MASK         (0xdeadbeef)
+
 enum pll_mode {
 	PLL_MODE_MIN =3D 0,
 	PLL_MODE_AUTOMATIC =3D PLL_MODE_MIN,
--
2.7.4