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From:   Zong Li <zong.li@sifive.com>
To:     paul.walmsley@sifive.com, palmer@dabbelt.com,
        aou@eecs.berkeley.edu, mturquette@baylibre.com, sboyd@kernel.org,
        yash.shah@sifive.com, linux-kernel@vger.kernel.org,
        linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org
Cc:     Zong Li <zong.li@sifive.com>
Subject: [PATCH 4/4] clk: sifive: Refactor __prci_clock array by using macro
Date:   Fri, 16 Oct 2020 17:18:26 +0800
Message-Id: <8ad64f9814137c5255d43d4ba670b5fcd15837ab.1602838910.git.zong.li@sifive.com>
In-Reply-To: <cover.1602838910.git.zong.li@sifive.com>
References: <cover.1602838910.git.zong.li@sifive.com>
MIME-Version: 1.0
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Precedence: bulk

Refactor code by using DEFINE_PRCI_CLOCK to define each clock
and reduce duplicate code.

Signed-off-by: Zong Li <zong.li@sifive.com>
---
 drivers/clk/sifive/fu540-prci.c  | 38 ++++++----------
 drivers/clk/sifive/fu540-prci.h  |  2 +-
 drivers/clk/sifive/fu740-prci.c  | 74 ++++++++++++--------------------
 drivers/clk/sifive/fu740-prci.h  |  2 +-
 drivers/clk/sifive/sifive-prci.c |  2 +-
 drivers/clk/sifive/sifive-prci.h | 10 ++++-
 6 files changed, 53 insertions(+), 75 deletions(-)

diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index 840b97bfff85..d43b9a9984f6 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -54,29 +54,19 @@ static const struct clk_ops sifive_fu540_prci_tlclksel_clk_ops = {
 	.recalc_rate = sifive_prci_tlclksel_recalc_rate,
 };
 
+DEFINE_PRCI_CLOCK(fu540, corepll, hfclk,
+		  &sifive_fu540_prci_wrpll_clk_ops, &__prci_corepll_data);
+DEFINE_PRCI_CLOCK(fu540, ddrpll, hfclk,
+		  &sifive_fu540_prci_wrpll_ro_clk_ops, &__prci_ddrpll_data);
+DEFINE_PRCI_CLOCK(fu540, gemgxlpll, hfclk,
+		  &sifive_fu540_prci_wrpll_clk_ops, &__prci_gemgxlpll_data);
+DEFINE_PRCI_CLOCK(fu540, tlclk, corepll,
+		  &sifive_fu540_prci_tlclksel_clk_ops, NULL);
+
 /* List of clock controls provided by the PRCI */
-struct __prci_clock __prci_init_clocks_fu540[] = {
-	[PRCI_CLK_COREPLL] = {
-		.name = "corepll",
-		.parent_name = "hfclk",
-		.ops = &sifive_fu540_prci_wrpll_clk_ops,
-		.pwd = &__prci_corepll_data,
-	},
-	[PRCI_CLK_DDRPLL] = {
-		.name = "ddrpll",
-		.parent_name = "hfclk",
-		.ops = &sifive_fu540_prci_wrpll_ro_clk_ops,
-		.pwd = &__prci_ddrpll_data,
-	},
-	[PRCI_CLK_GEMGXLPLL] = {
-		.name = "gemgxlpll",
-		.parent_name = "hfclk",
-		.ops = &sifive_fu540_prci_wrpll_clk_ops,
-		.pwd = &__prci_gemgxlpll_data,
-	},
-	[PRCI_CLK_TLCLK] = {
-		.name = "tlclk",
-		.parent_name = "corepll",
-		.ops = &sifive_fu540_prci_tlclksel_clk_ops,
-	},
+struct __prci_clock *__prci_init_clocks_fu540[] = {
+	[PRCI_CLK_COREPLL]	= &fu540_corepll,
+	[PRCI_CLK_DDRPLL]	= &fu540_ddrpll,
+	[PRCI_CLK_GEMGXLPLL]	= &fu540_gemgxlpll,
+	[PRCI_CLK_TLCLK]	= &fu540_tlclk,
 };
diff --git a/drivers/clk/sifive/fu540-prci.h b/drivers/clk/sifive/fu540-prci.h
index c8271efa7bdc..281200cd8848 100644
--- a/drivers/clk/sifive/fu540-prci.h
+++ b/drivers/clk/sifive/fu540-prci.h
@@ -11,7 +11,7 @@
 
 #define NUM_CLOCK_FU540	4
 
-extern struct __prci_clock __prci_init_clocks_fu540[NUM_CLOCK_FU540];
+extern struct __prci_clock *__prci_init_clocks_fu540[NUM_CLOCK_FU540];
 
 static const struct prci_clk_desc prci_clk_fu540 = {
 	.clks = __prci_init_clocks_fu540,
diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c
index 3b87e273c3eb..676cad2c3886 100644
--- a/drivers/clk/sifive/fu740-prci.c
+++ b/drivers/clk/sifive/fu740-prci.c
@@ -71,52 +71,32 @@ static const struct clk_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = {
 	.recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate,
 };
 
+
+DEFINE_PRCI_CLOCK(fu740, corepll, hfclk,
+		  &sifive_fu740_prci_wrpll_clk_ops, &__prci_corepll_data);
+DEFINE_PRCI_CLOCK(fu740, ddrpll, hfclk,
+		  &sifive_fu740_prci_wrpll_ro_clk_ops, &__prci_ddrpll_data);
+DEFINE_PRCI_CLOCK(fu740, gemgxlpll, hfclk,
+		  &sifive_fu740_prci_wrpll_clk_ops, &__prci_gemgxlpll_data);
+DEFINE_PRCI_CLOCK(fu740, dvfscorepll, hfclk,
+		  &sifive_fu740_prci_wrpll_clk_ops, &__prci_dvfscorepll_data);
+DEFINE_PRCI_CLOCK(fu740, hfpclkpll, hfclk,
+		  &sifive_fu740_prci_wrpll_clk_ops, &__prci_hfpclkpll_data);
+DEFINE_PRCI_CLOCK(fu740, cltxpll, hfclk,
+		  &sifive_fu740_prci_wrpll_clk_ops, &__prci_cltxpll_data);
+DEFINE_PRCI_CLOCK(fu740, tlclk, corepll,
+		  &sifive_fu740_prci_tlclksel_clk_ops, NULL);
+DEFINE_PRCI_CLOCK(fu740, pclk, hfpclkpll,
+		  &sifive_fu740_prci_hfpclkplldiv_clk_ops, NULL);
+
 /* List of clock controls provided by the PRCI */
-struct __prci_clock __prci_init_clocks_fu740[] = {
-	[PRCI_CLK_COREPLL] = {
-		.name = "corepll",
-		.parent_name = "hfclk",
-		.ops = &sifive_fu740_prci_wrpll_clk_ops,
-		.pwd = &__prci_corepll_data,
-	},
-	[PRCI_CLK_DDRPLL] = {
-		.name = "ddrpll",
-		.parent_name = "hfclk",
-		.ops = &sifive_fu740_prci_wrpll_ro_clk_ops,
-		.pwd = &__prci_ddrpll_data,
-	},
-	[PRCI_CLK_GEMGXLPLL] = {
-		.name = "gemgxlpll",
-		.parent_name = "hfclk",
-		.ops = &sifive_fu740_prci_wrpll_clk_ops,
-		.pwd = &__prci_gemgxlpll_data,
-	},
-	[PRCI_CLK_DVFSCOREPLL] = {
-		.name = "dvfscorepll",
-		.parent_name = "hfclk",
-		.ops = &sifive_fu740_prci_wrpll_clk_ops,
-		.pwd = &__prci_dvfscorepll_data,
-	},
-	[PRCI_CLK_HFPCLKPLL] = {
-		.name = "hfpclkpll",
-		.parent_name = "hfclk",
-		.ops = &sifive_fu740_prci_wrpll_clk_ops,
-		.pwd = &__prci_hfpclkpll_data,
-	},
-	[PRCI_CLK_CLTXPLL] = {
-		.name = "cltxpll",
-		.parent_name = "hfclk",
-		.ops = &sifive_fu740_prci_wrpll_clk_ops,
-		.pwd = &__prci_cltxpll_data,
-	},
-	[PRCI_CLK_TLCLK] = {
-		.name = "tlclk",
-		.parent_name = "corepll",
-		.ops = &sifive_fu740_prci_tlclksel_clk_ops,
-	},
-	[PRCI_CLK_PCLK] = {
-		.name = "pclk",
-		.parent_name = "hfpclkpll",
-		.ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops,
-	},
+struct __prci_clock *__prci_init_clocks_fu740[] = {
+	[PRCI_CLK_COREPLL]	= &fu740_corepll,
+	[PRCI_CLK_DDRPLL]	= &fu740_ddrpll,
+	[PRCI_CLK_GEMGXLPLL]	= &fu740_gemgxlpll,
+	[PRCI_CLK_DVFSCOREPLL]	= &fu740_dvfscorepll,
+	[PRCI_CLK_HFPCLKPLL]	= &fu740_hfpclkpll,
+	[PRCI_CLK_CLTXPLL]	= &fu740_cltxpll,
+	[PRCI_CLK_TLCLK]	= &fu740_tlclk,
+	[PRCI_CLK_PCLK]		= &fu740_pclk,
 };
diff --git a/drivers/clk/sifive/fu740-prci.h b/drivers/clk/sifive/fu740-prci.h
index 13ef971f7764..3f03295f719a 100644
--- a/drivers/clk/sifive/fu740-prci.h
+++ b/drivers/clk/sifive/fu740-prci.h
@@ -11,7 +11,7 @@
 
 #define NUM_CLOCK_FU740	8
 
-extern struct __prci_clock __prci_init_clocks_fu740[NUM_CLOCK_FU740];
+extern struct __prci_clock *__prci_init_clocks_fu740[NUM_CLOCK_FU740];
 
 static const struct prci_clk_desc prci_clk_fu740 = {
 	.clks = __prci_init_clocks_fu740,
diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c
index 4098dbc5881a..2ef3f9f91b33 100644
--- a/drivers/clk/sifive/sifive-prci.c
+++ b/drivers/clk/sifive/sifive-prci.c
@@ -431,7 +431,7 @@ static int __prci_register_clocks(struct device *dev, struct __prci_data *pd,
 
 	/* Register PLLs */
 	for (i = 0; i < desc->num_clks; ++i) {
-		pic = &(desc->clks[i]);
+		pic = desc->clks[i];
 
 		init.name = pic->name;
 		init.parent_names = &pic->parent_name;
diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h
index bc0646bc9c3e..e6c9f72e20de 100644
--- a/drivers/clk/sifive/sifive-prci.h
+++ b/drivers/clk/sifive/sifive-prci.h
@@ -253,6 +253,14 @@ struct __prci_clock {
 	struct __prci_data *pd;
 };
 
+#define DEFINE_PRCI_CLOCK(_platform, _name, _parent, _ops, _pwd)	\
+	static struct __prci_clock _platform##_##_name = {		\
+		.name = #_name,						\
+		.parent_name = #_parent,				\
+		.ops = _ops,						\
+		.pwd = _pwd,						\
+	}								\
+
 #define clk_hw_to_prci_clock(pwd) container_of(pwd, struct __prci_clock, hw)
 
 /*
@@ -261,7 +269,7 @@ struct __prci_clock {
  * @num_clks: the number of element of clks
  */
 struct prci_clk_desc {
-	struct __prci_clock *clks;
+	struct __prci_clock **clks;
 	size_t num_clks;
 };
 
-- 
2.28.0