Received: by 2002:a05:6a10:6744:0:0:0:0 with SMTP id w4csp1232829pxu; Fri, 16 Oct 2020 07:12:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwQFuVWo9L5+YP+kAOCGVNvneSQYkmcbLFg/4zdq9iPFu1dHF76sgKWKx2aEzaUTKB99AZT X-Received: by 2002:aa7:cacd:: with SMTP id l13mr4085497edt.177.1602857575250; Fri, 16 Oct 2020 07:12:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1602857575; cv=none; d=google.com; s=arc-20160816; b=X5R5ulQPJDvQ1fv3rjb6VvJm0s73NNO0fpKnVPF/L/iAfKbFbq3iFz8jS8h6N2nP6B H5QeESmzbM3HZicxeTeb5hmeciwUtC8W+EY2YI7LIvIZ+L1HmZVBI2nQzvRu/Sn+/+Wy spcMd6dhQ10xLnF7lGgAuxejf9TaH4NJpMnSfwZyvTaHwiV/efNX5jLObOB9MuLF2ucp Zl0EalUEEdseSV9AwXhPjDSuYaU5+QR+9XMXD6B7QStUvP0TBHX0teIfPqNhMv5APIp8 q1fy0dGr/7cGUud+rxnqb2BtqpkTIUOEhH+Nnn0fjRJYxayvQBtej5JRznQbIWktN9BG FG8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:ironport-sdr:ironport-sdr; bh=PTVxx8uF3y934w1xDKCqH5r9BpgtWYNiOyYCxi+Aoow=; b=MWYFnFqGRvpkt/pBZreyixMjjZKdt65U5tGVsT9XE3bBLBtq2QFBQithJx3VQinUXL 8FI83YcqyhDedJ82xzyYfTLqV0/hGguPYCxh8HQNHMsUV4bBKhQa/RdFB+A81X5VCwE0 f+b99cRmg9aahLPpX1qMuQGNQYrIsJOPSqYmMVcNiiC95bzZdv5DRrTXXFLOxuwaplbe puCeCv83fRb+eYw9V4Q4CwffkAEq2iLao6WbkOolcXRpu4nkseXHNC7lpE6s5SCyk8zR WQxHgigWyMCbQyhnXNLxkNtu6e2p9+FpHjzAiPBDaBm891fY3ZAhPiiVVOsP2NhRrZHP eQvQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id do2si1899496ejc.215.2020.10.16.07.12.32; Fri, 16 Oct 2020 07:12:55 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405818AbgJPJcQ (ORCPT + 99 others); Fri, 16 Oct 2020 05:32:16 -0400 Received: from mga07.intel.com ([134.134.136.100]:44810 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2405685AbgJPJcO (ORCPT ); Fri, 16 Oct 2020 05:32:14 -0400 IronPort-SDR: v3iy7ApjClUBPxbRgfuVF0SH3NYbxCyBkPDy7TSIABhVrw3eSNWb40au6LAg6bf0fbODlWnAWO XK3mPzW8i0xg== X-IronPort-AV: E=McAfee;i="6000,8403,9775"; a="230763033" X-IronPort-AV: E=Sophos;i="5.77,382,1596524400"; d="scan'208";a="230763033" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2020 02:32:12 -0700 IronPort-SDR: Mp6Tp/RETcAlV94DqN0Aos0Zaq8oC3zpLNY589c/nNqmrGOFmO/hSoZd8NsJSSjHbdFJzrYj5Q LNNcHfajz46g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,382,1596524400"; d="scan'208";a="522175941" Received: from sgsxdev004.isng.intel.com (HELO localhost) ([10.226.88.13]) by fmsmga005.fm.intel.com with ESMTP; 16 Oct 2020 02:32:09 -0700 From: "Ramuthevar,Vadivel MuruganX" To: vigneshr@ti.com, tudor.ambarus@microchip.com, broonie@kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, miquel.raynal@bootlin.com, simon.k.r.goldschmidt@gmail.com, dinguyen@kernel.org, richard@nod.at, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, Ramuthevar Vadivel Murugan Subject: [PATCH v1 6/6] spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC Date: Fri, 16 Oct 2020 17:31:38 +0800 Message-Id: <20201016093138.28871-7-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20201016093138.28871-1-vadivel.muruganx.ramuthevar@linux.intel.com> References: <20201016093138.28871-1-vadivel.muruganx.ramuthevar@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ramuthevar Vadivel Murugan Add multiple chipselect support for Intel LGM SoCs, currently QSPI-NOR and QSPI-NAND supported. Signed-off-by: Ramuthevar Vadivel Murugan --- drivers/spi/spi-cadence-quadspi.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 3d017b484114..3bf6d3697631 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -38,6 +38,7 @@ /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) +#define CQSPI_SUPPORTS_MULTI_CHIPSELECT BIT(1) struct cqspi_st; @@ -75,6 +76,7 @@ struct cqspi_st { bool is_decoded_cs; u32 fifo_depth; u32 fifo_width; + u32 num_chipselect; bool rclk_en; u32 trigger_address; u32 wr_delay; @@ -1070,6 +1072,14 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqspi) return -ENXIO; } + if (!cqspi->use_direct_mode) { + if (of_property_read_u32(np, "num-chipselect", + &cqspi->num_chipselect)) { + dev_err(dev, "couldn't determine number of cs\n"); + return -ENXIO; + } + } + cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); return 0; @@ -1307,6 +1317,9 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->current_cs = -1; cqspi->sclk = 0; + if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT) + master->num_chipselect = cqspi->num_chipselect; + ret = cqspi_setup_flash(cqspi); if (ret) { dev_err(dev, "failed to setup flash parameters %d\n", ret); @@ -1396,6 +1409,7 @@ static const struct cqspi_driver_platdata am654_ospi = { }; static const struct cqspi_driver_platdata intel_lgm_qspi = { + .hwcaps_mask = CQSPI_SUPPORTS_MULTI_CHIPSELECT, .quirks = CQSPI_DISABLE_DAC_MODE, }; -- 2.11.0