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Date:   Sun, 18 Oct 2020 10:50:25 -0400
From:   William Breathitt Gray <vilhelm.gray@gmail.com>
To:     David Lechner <david@lechnology.com>
Cc:     jic23@kernel.org, kamel.bouhara@bootlin.com, gwendal@chromium.org,
        alexandre.belloni@bootlin.com, linux-iio@vger.kernel.org,
        linux-kernel@vger.kernel.org,
        linux-stm32@st-md-mailman.stormreply.com,
        linux-arm-kernel@lists.infradead.org, syednwaris@gmail.com,
        patrick.havelange@essensium.com, fabrice.gasnier@st.com,
        mcoquelin.stm32@gmail.com, alexandre.torgue@st.com
Subject: Re: [PATCH v5 5/5] counter: 104-quad-8: Add IRQ support for the
 ACCES 104-QUAD-8
Message-ID: <20201018145025.GC231549@shinobu>
References: <cover.1601170670.git.vilhelm.gray@gmail.com>
 <7a829fe8cba3ae222796328f832bd2546769e6ac.1601170670.git.vilhelm.gray@gmail.com>
 <a0e54a35-eed6-a938-dd4e-4f602d3b50c0@lechnology.com>
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On Tue, Oct 13, 2020 at 07:13:32PM -0500, David Lechner wrote:
> On 9/26/20 9:18 PM, William Breathitt Gray wrote:
> > +static irqreturn_t quad8_irq_handler(int irq, void *quad8iio)
> > +{
> > +	struct quad8_iio *const priv =3D quad8iio;
> > +	const unsigned long base =3D priv->base;
> > +	unsigned long irq_status;
> > +	unsigned long channel;
> > +	u8 event;
> > +	int err;
> > +
> > +	irq_status =3D inb(base + QUAD8_REG_INTERRUPT_STATUS);
> > +	if (!irq_status)
> > +		return IRQ_NONE;
> > +
> > +	for_each_set_bit(channel, &irq_status, QUAD8_NUM_COUNTERS) {
> > +		switch (priv->irq_trigger[channel]) {
> > +		case 0:
> > +			event =3D COUNTER_EVENT_OVERFLOW;
> > +				break;
> > +		case 1:
> > +			event =3D COUNTER_EVENT_THRESHOLD;
> > +				break;
> > +		case 2:
> > +			event =3D COUNTER_EVENT_OVERFLOW_UNDERFLOW;
> > +				break;
> > +		case 3:
> > +			event =3D COUNTER_EVENT_INDEX;
> > +				break;
> > +		default:
> > +			/* We should never reach here */
> > +			return -EINVAL;
>=20
> This is not a valid return value for an IRQ handler. Maybe WARN_ONCE inst=
ead?

Ack.

> > +		}
> > +		err =3D counter_push_event(&priv->counter, event, channel);
> > +		if (err)
> > +			return err;
>=20
> Same here. Otherwise, I think we could end up with interrupts in an endle=
ss
> loop since the interrupt would never be cleared.

Good point, I'll change this and the one above.

William Breathitt Gray

> > +	}
> > +
> > +	/* Clear pending interrupts on device */
> > +	outb(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, base + QUAD8_REG_CHAN_OP);
> > +
> > +	return IRQ_HANDLED;
> > +}
> > +
>=20

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Content-Type: application/pgp-signature; name="signature.asc"

-----BEGIN PGP SIGNATURE-----

iQIzBAABCgAdFiEEk5I4PDJ2w1cDf/bghvpINdm7VJIFAl+MVjEACgkQhvpINdm7
VJJ/2g/9H84UNACWIgJbKmcgPdOuv42qHwZ0jla3LA3Sa/Le+jjyRPXhlC0po31D
Q02H/GXunXfanDa3dRcI+4wKobRonBxnD4qvQcv9PMY4KWIxiqRUzIToz6PG4Frl
U1lod6lMw7tmTBAov69D+faZv7q46UiuJ4fNpZjzhgy+Ut78SsR5x/FSM8W+y2Xe
VeWYX3MPk7xrVMDdwFZN8x8lCKUgwlDBIPgLW9SoGaoqJfXSa4EZejluUo8jztlz
yehC6XuGu0gkIvfWq2PTqAX8wciFoxv1xHZ0+4Rgyw+7qW3sXFT+rWGygxiyxAe6
qr1DJ9r9JkSLTNYuMkdn2g6jhoH98mrkSbhi5uwf34H5At874zqFI3tcgG8s05fO
drKQeA1WjVDp7TaEF1OfXfqKkuiKL0+YUB6fxQpZ53KvT2tRSSl/9A7z/JCkGyKX
8pSntpr1rI9ZR9dxzk6nblOoZX7KYO1K4hZ0Eby1E3YI/y7IrzAADYuB2t0MzVfn
qQMXT8LzKtaE/pIQk9IfnOevFFKhfchknxxtXW4I0ak6RlKuo7Ai7IPUeuQvukEK
pM63pZ41G5Y6uzefTecb+kg33cVMC2shKU2hRJYzL0o5z2CcQUAyCKuFuBM1k4LX
sxYRf3wetepvzBMF6YUzCpcR8fBQP/kuVR3PYd5sche8IpphpK0=
=xuQj
-----END PGP SIGNATURE-----

--UPT3ojh+0CqEDtpF--