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[81.185.167.26]) by smtp.gmail.com with ESMTPSA id a3sm114182wmb.46.2020.10.19.07.07.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Oct 2020 07:07:15 -0700 (PDT) From: Fabien Parent To: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pwm@vger.kernel.org Cc: matthias.bgg@gmail.com, robh+dt@kernel.org, lee.jones@linaro.org, u.kleine-koenig@pengutronix.de, thierry.reding@gmail.com, Fabien Parent Subject: [PATCH 4/5] arm64: dts: mediatek: mt8183: add pwm node Date: Mon, 19 Oct 2020 16:07:04 +0200 Message-Id: <20201019140705.1518822-5-fparent@baylibre.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201019140705.1518822-1-fparent@baylibre.com> References: <20201019140705.1518822-1-fparent@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org MT8183 SoC has 4 PWMs. Add the pwm node in order to support them. Signed-off-by: Fabien Parent --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 9a3cf95676e1..290d15dd9490 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -709,6 +709,20 @@ mmc1: mmc@11240000 { status = "disabled"; }; + pwm0: pwm@11006000 { + compatible = "mediatek,mt8183-pwm"; + reg = <0 0x11006000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&infracfg CLK_INFRA_PWM>, + <&infracfg CLK_INFRA_PWM_HCLK>, + <&infracfg CLK_INFRA_PWM1>, + <&infracfg CLK_INFRA_PWM2>, + <&infracfg CLK_INFRA_PWM3>, + <&infracfg CLK_INFRA_PWM4>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3", + "pwm4"; + }; + efuse: efuse@11f10000 { compatible = "mediatek,mt8183-efuse", "mediatek,efuse"; -- 2.28.0