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Date:   Mon, 19 Oct 2020 17:13:31 +0100
From:   Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To:     "Z.q. Hou" <zhiqiang.hou@nxp.com>
Cc:     Kishon Vijay Abraham I <kishon@ti.com>,
        Rob Herring <robh@kernel.org>,
        Gustavo Pimentel <Gustavo.Pimentel@synopsys.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        PCI <linux-pci@vger.kernel.org>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Michael Walle <michael@walle.cc>,
        Ard Biesheuvel <ardb@kernel.org>
Subject: Re: [PATCH] PCI: dwc: Added link up check in map_bus of
 dw_child_pcie_ops
Message-ID: <20201019161311.GA9813@e121166-lin.cambridge.arm.com>
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On Mon, Oct 12, 2020 at 04:41:11AM +0000, Z.q. Hou wrote:

[...]

> > >> Yeah, I don't see any registers in the DRA7x PCIe wrapper for
> > >> disabling error forwarding.
> > >
> > > It's a DWC port logic register AFAICT, but perhaps not present in all
> > versions.
> > 
> > Okay. I see there's a register PCIECTRL_PL_AXIS_SLV_ERR_RESP which has a
> > reset value of 0.
> > 
> > It has four bit-fields, RESET_TIMEOUT_ERR_MAP, NO_VID_ERR_MAP,
> > DBI_ERR_MAP and SLAVE_ERR_MAP. I'm not seeing any difference in
> > behavior if I set all these bits. Maybe it requires platform support too. I'll
> > check this with our design team.
> 
> In DWC v4.40a databook, there is a bit AMBA_ERROR_RESPONSE_GLOBAL
> which controls if enable the error forwarding. The *MAP bits only
> determine which error (SLVERR or DECERR) will be forwarded to AXI/AHB
> bus.

I have not seen a follow-up to this but I would like to, still keen
on avoiding this patch if possible - if this is port logic it should
be common across controllers implementations I assume.

Gustavo, Kishon ?

Thanks,
Lorenzo

> Thanks,
> Zhiqiang
> 
> > 
> > Meanwhile would it be okay to add linkup check atleast for DRA7X so that
> > we could have it booting in linux-next?
> > 
> > Thanks
> > Kishon