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[23.128.96.18]) by mx.google.com with ESMTP id v8si679607ejx.1.2020.10.19.23.54.31; Mon, 19 Oct 2020 23:54:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728587AbgJSRsi (ORCPT + 99 others); Mon, 19 Oct 2020 13:48:38 -0400 Received: from mga03.intel.com ([134.134.136.65]:10188 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728496AbgJSRsi (ORCPT ); Mon, 19 Oct 2020 13:48:38 -0400 IronPort-SDR: Op9a7yxidNbqMoSnVTTs+Wp3ZQQes9r+JfFctrYeGGpXcIpVlrZA0wnQbbBZA/BZX0OQCDueHZ mEsoO5a6W79A== X-IronPort-AV: E=McAfee;i="6000,8403,9779"; a="167153775" X-IronPort-AV: E=Sophos;i="5.77,395,1596524400"; d="scan'208";a="167153775" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2020 10:48:37 -0700 IronPort-SDR: BoyhJy++jKGmax4Q37KULZt0DTtaSKc3/w4/iikvB3JL+Zp3Sze8s40dwyu8OpCiWVMUPpmLt4 vZQjqr/rA4dg== X-IronPort-AV: E=Sophos;i="5.77,395,1596524400"; d="scan'208";a="522075483" Received: from haixinlu-mobl1.amr.corp.intel.com (HELO [10.212.84.56]) ([10.212.84.56]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2020 10:48:35 -0700 Subject: Re: [PATCH v39 05/24] x86/sgx: Add wrappers for ENCLS leaf functions To: Sean Christopherson Cc: Jarkko Sakkinen , x86@kernel.org, linux-sgx@vger.kernel.org, linux-kernel@vger.kernel.org, Jethro Beekman , Darren Kenny , akpm@linux-foundation.org, andriy.shevchenko@linux.intel.com, asapek@google.com, bp@alien8.de, cedric.xing@intel.com, chenalexchen@google.com, conradparker@google.com, cyhanish@google.com, haitao.huang@intel.com, kai.huang@intel.com, kai.svahn@intel.com, kmoy@google.com, ludloff@google.com, luto@kernel.org, nhorman@redhat.com, npmccallum@redhat.com, puiterwijk@redhat.com, rientjes@google.com, tglx@linutronix.de, yaozhangx@google.com, mikko.ylinen@intel.com References: <20201003045059.665934-1-jarkko.sakkinen@linux.intel.com> <20201003045059.665934-6-jarkko.sakkinen@linux.intel.com> <20201019173840.GA22119@linux.intel.com> From: Dave Hansen Autocrypt: addr=dave.hansen@intel.com; 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Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20201019173840.GA22119@linux.intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/19/20 10:38 AM, Sean Christopherson wrote: >>> +static inline bool encls_failed(int ret) >>> +{ >>> + int epcm_trapnr; >>> + >>> + if (boot_cpu_has(X86_FEATURE_SGX2)) >>> + epcm_trapnr = X86_TRAP_PF; >>> + else >>> + epcm_trapnr = X86_TRAP_GP; >> So, the SDM makes it sound like the only thing that changes from >> SGX1->SGX2 is the ENCLS leafs supported. Since the kernel doesn't use >> any SGX2 leaf functions, this would imply there is some other >> architecture change which is visible. *But* I don't see any evidence of >> this in the SDM, at least from a quick scan. >> >> Why is this here? > SGX1 CPUs take an erratum on the #PF behavior, e.g. "KBW90 Violation of Intel > SGX Access-Control Requirements Produce #GP Instead of #PF". > > https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-e3-1200v6-spec-update.pdf OK, but that's only for "Intel ® Xeon ® E3-1200 v6 Processor Family", specifically stepping B-0. That's far from a broad erratum. I *see* it in other errata lists, but I still think this is too broad. Also, what if a hypervisor masks the SGX2 cpuid bit on SGX2-capable hardware? Won't the hardware still exhibit the erratum? I don't think we can control model-specific errata behavior with an architectural CPUID bit.