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Date:   Tue, 20 Oct 2020 10:55:27 +0100
From:   Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To:     "Z.q. Hou" <zhiqiang.hou@nxp.com>
Cc:     Kishon Vijay Abraham I <kishon@ti.com>,
        Bjorn Helgaas <helgaas@kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        "robh@kernel.org" <robh@kernel.org>,
        "bhelgaas@google.com" <bhelgaas@google.com>,
        "gustavo.pimentel@synopsys.com" <gustavo.pimentel@synopsys.com>
Subject: Re: [PATCH] PCI: dwc: Added link up check in map_bus of
 dw_child_pcie_ops
Message-ID: <20201020095527.GA21814@e121166-lin.cambridge.arm.com>
References: <20200916054130.8685-1-Zhiqiang.Hou@nxp.com>
 <20201015224738.GA24466@bjorn-Precision-5520>
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On Tue, Oct 20, 2020 at 02:13:13AM +0000, Z.q. Hou wrote:

[...]

> > > For NXP Layerscape platforms (the ls1028a and ls2088a are also NXP
> > Layerscape platform), as the error response to AXI/AHB was enabled, it will
> > get UR error and trigger SError on AXI bus when it accesses a non-existent
> > BDF on a link down bus. I'm not clear about how it happens on dra7xxx and
> > imx6, since they doesn't enable the error response to AXI/AHB.
> > 
> > That's exactly the case with DRA7xx as the error response is enabled by
> > default in the platform integration.
> 
> Got feedback from the imx6 owner that imx6 like the dra7xx has the
> error response enabled by default.  Now it's clear that the problem on
> all these platforms is the same.

On IMX6, enabled by default and read-only ? Or it can be changed ? What's
the plan for layerscape on this matter ?

Lorenzo