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a="146393725" X-IronPort-AV: E=Sophos;i="5.77,395,1596524400"; d="scan'208";a="146393725" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2020 13:21:11 -0700 IronPort-SDR: 1EXuQhFjza0k+Lt3XlMfKBwE0vXsm16ZZXv0P9NcdvClM7Vg8K2TXPNzPTnboTDNAle6V8ZGNr C2k39n58aBlQ== X-IronPort-AV: E=Sophos;i="5.77,395,1596524400"; d="scan'208";a="522118229" Received: from haixinlu-mobl1.amr.corp.intel.com (HELO [10.212.84.56]) ([10.212.84.56]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2020 13:21:10 -0700 Subject: Re: [PATCH v39 12/24] x86/sgx: Add SGX_IOC_ENCLAVE_CREATE To: Jarkko Sakkinen Cc: x86@kernel.org, linux-sgx@vger.kernel.org, linux-kernel@vger.kernel.org, Jethro Beekman , Haitao Huang , Chunyang Hui , Jordan Hand , Nathaniel McCallum , Seth Moore , Darren Kenny , Sean Christopherson , Suresh Siddha , akpm@linux-foundation.org, andriy.shevchenko@linux.intel.com, asapek@google.com, bp@alien8.de, cedric.xing@intel.com, chenalexchen@google.com, conradparker@google.com, cyhanish@google.com, haitao.huang@intel.com, kai.huang@intel.com, kai.svahn@intel.com, kmoy@google.com, ludloff@google.com, luto@kernel.org, nhorman@redhat.com, puiterwijk@redhat.com, rientjes@google.com, tglx@linutronix.de, yaozhangx@google.com, mikko.ylinen@intel.com References: <20201003045059.665934-1-jarkko.sakkinen@linux.intel.com> <20201003045059.665934-13-jarkko.sakkinen@linux.intel.com> <5f194bf0-ced1-66e1-b6a2-503741a3e7f1@intel.com> <20201018042633.GI68722@linux.intel.com> From: Dave Hansen Autocrypt: addr=dave.hansen@intel.com; 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Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20201018042633.GI68722@linux.intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/17/20 9:26 PM, Jarkko Sakkinen wrote: ... >>> +static int sgx_validate_secs(const struct sgx_secs *secs) >>> +{ >> >> What's the overall point of this function? Does it avoid a #GP from an >> instruction later? >> >> Does all of the 'secs' content come from userspace? > > Yes it does avoid #GP, and all the data comes from the user space. Please comment the function to indicate this. But, in general, why do we care to avoid a #GP? Is it just because we don't have infrastructure in-kernel to suppress the resulting panic()? >>> + u64 max_size = (secs->attributes & SGX_ATTR_MODE64BIT) ? >>> + sgx_encl_size_max_64 : sgx_encl_size_max_32; >>> + >>> + if (secs->size < (2 * PAGE_SIZE) || !is_power_of_2(secs->size)) >>> + return -EINVAL; >>> + >>> + if (secs->base & (secs->size - 1)) >>> + return -EINVAL; >>> + >>> + if (secs->miscselect & sgx_misc_reserved_mask || >>> + secs->attributes & sgx_attributes_reserved_mask || >>> + secs->xfrm & sgx_xfrm_reserved_mask) >>> + return -EINVAL; >>> + >>> + if (secs->size > max_size) >>> + return -EINVAL; >>> + >>> + if (!(secs->xfrm & XFEATURE_MASK_FP) || >>> + !(secs->xfrm & XFEATURE_MASK_SSE) || >>> + (((secs->xfrm >> XFEATURE_BNDREGS) & 1) != ((secs->xfrm >> XFEATURE_BNDCSR) & 1))) >>> + return -EINVAL; >>> + >>> + if (!secs->ssa_frame_size) >>> + return -EINVAL; >>> + >>> + if (sgx_calc_ssa_frame_size(secs->miscselect, secs->xfrm) > secs->ssa_frame_size) >>> + return -EINVAL; >>> + >>> + if (memchr_inv(secs->reserved1, 0, sizeof(secs->reserved1)) || >>> + memchr_inv(secs->reserved2, 0, sizeof(secs->reserved2)) || >>> + memchr_inv(secs->reserved3, 0, sizeof(secs->reserved3)) || >>> + memchr_inv(secs->reserved4, 0, sizeof(secs->reserved4))) >>> + return -EINVAL; >>> + >>> + return 0; >>> +} >> >> I think it would be nice to at least have one comment per condition to >> explain what's going on there. ... >>> +static int sgx_encl_create(struct sgx_encl *encl, struct sgx_secs *secs) >>> +{ >>> + struct sgx_epc_page *secs_epc; >>> + struct sgx_pageinfo pginfo; >>> + struct sgx_secinfo secinfo; >>> + unsigned long encl_size; >>> + struct file *backing; >>> + long ret; >>> + >>> + if (sgx_validate_secs(secs)) { >>> + pr_debug("invalid SECS\n"); >>> + return -EINVAL; >>> + } >>> + >>> + /* The extra page goes to SECS. */ >>> + encl_size = secs->size + PAGE_SIZE; >>> + >>> + backing = shmem_file_setup("SGX backing", encl_size + (encl_size >> 5), >>> + VM_NORESERVE); >> >> What's the >>5 adjustment for? > > The backing storage stores not only the swapped page but also > Paging Crypto MetaData (PCMD) structure. It essentially contains > a CPU encrypted MAC for a page. > > The MAC is over page version and data. The version is stored in > a EPC page called Version Array (VA) page. > > Both of these are needed by ENCLS[ELDU]. /* * SGX backing storage needs to contain space for both the * EPC data and some metadata called the Paging Crypto * MetaData (PCMD). The PCMD needs 128b of storage for each * page. */ Also, the MAC is a fixed size, right? Let's say that x86 got a larger page size in the future. Would this number be 128b or PAGE_SIZE/32? If it's a fixed size, I'd write: size = encl_size; size += (encl_size / PAGE_SIZE) * SGX_PCPD_PER_PAGE; If it really is 1/32nd, I'd write size += encl_size / SGX_PCPD_RATIO; or something. Either way, the >>5 is total magic and needs comments and fixing. >>> +long sgx_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) >>> +{ >>> + struct sgx_encl *encl = filep->private_data; >>> + int ret, encl_flags; >>> + >>> + encl_flags = atomic_fetch_or(SGX_ENCL_IOCTL, &encl->flags); >>> + if (encl_flags & SGX_ENCL_IOCTL) >>> + return -EBUSY; >> >> Is the SGX_ENCL_IOCTL bit essentially just a lock to single-thread >> ioctl()s? Should we name it as such? > > Yes. It makes the concurrency overally easier if we can assume that > only a single ioctl is in progress. There is no good reason to do > them in parallel. > > E.g. when you add pages you want to do that serially because the > order changes the MRENCLAVE. There are also hardware concurrency requirements, right? A bunch of the SGX functions seem not not even support being called in parallel. > So should I rename it as SGX_ENCL_IOCTL_LOCKED? I'd rather not see hand-rolled locking primitives frankly.