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dmarc=pass action=none header.from=aspeedtech.com; dkim=pass header.d=aspeedtech.com; arc=none Received: from HK0PR06MB3779.apcprd06.prod.outlook.com (2603:1096:203:b8::10) by HK2PR06MB3250.apcprd06.prod.outlook.com (2603:1096:202:31::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3477.25; Tue, 20 Oct 2020 06:03:32 +0000 Received: from HK0PR06MB3779.apcprd06.prod.outlook.com ([fe80::a1a1:8859:d07a:2473]) by HK0PR06MB3779.apcprd06.prod.outlook.com ([fe80::a1a1:8859:d07a:2473%3]) with mapi id 15.20.3477.028; Tue, 20 Oct 2020 06:03:32 +0000 From: ChiaWei Wang To: "lee.jones@linaro.org" , "robh+dt@kernel.org" , "joel@jms.id.au" , "andrew@aj.id.au" , "minyard@acm.org" , "arnd@arndb.de" , "gregkh@linuxfoundation.org" , "linus.walleij@linaro.org" , "haiyue.wang@linux.intel.com" , "cyrilbur@gmail.com" , "rlippert@google.com" , "linux-arm-kernel@lists.infradead.org" , "linux-aspeed@lists.ozlabs.org" , "linux-kernel@vger.kernel.org" , "openbmc@lists.ozlabs.org" , "linux-gpio@vger.kernel.org" CC: BMC-SW Subject: RE: [PATCH v2 0/5] Remove LPC register partitioning Thread-Topic: [PATCH v2 0/5] Remove LPC register partitioning Thread-Index: AQHWmvF39eweRWKA/USnDpx5+4lpz6mgFZog Date: Tue, 20 Oct 2020 06:03:32 +0000 Message-ID: References: <20201005082806.28899-1-chiawei_wang@aspeedtech.com> In-Reply-To: <20201005082806.28899-1-chiawei_wang@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: zh-TW X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: linaro.org; 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Thanks. Chiawei > -----Original Message----- > From: ChiaWei Wang > Sent: Monday, October 5, 2020 4:28 PM > To: lee.jones@linaro.org; robh+dt@kernel.org; joel@jms.id.au; > andrew@aj.id.au; minyard@acm.org; arnd@arndb.de; > gregkh@linuxfoundation.org; linus.walleij@linaro.org; > haiyue.wang@linux.intel.com; cyrilbur@gmail.com; rlippert@google.com; > linux-arm-kernel@lists.infradead.org; linux-aspeed@lists.ozlabs.org; > linux-kernel@vger.kernel.org; openbmc@lists.ozlabs.org; > linux-gpio@vger.kernel.org > Subject: [PATCH v2 0/5] Remove LPC register partitioning > > The LPC controller has no concept of the BMC and the Host partitions. > The incorrect partitioning can impose unnecessary range restrictions on > register access through the syscon regmap interface. > > For instance, HICRB contains the I/O port address configuration of KCS channel > 1/2. However, the KCS#1/#2 drivers cannot access HICRB as it is located at the > other LPC partition. > > In addition, to be backward compatible, the newly added HW control bits could > be located at any reserved bits over the LPC addressing space. > > Thereby, this patch series aims to remove the LPC partitioning for better driver > development and maintenance. > > > Changes since v1: > - Add the fix to the aspeed-lpc binding documentation. > > Chia-Wei, Wang (5): > ARM: dts: Remove LPC BMC and Host partitions > soc: aspeed: Fix LPC register offsets > ipmi: kcs: aspeed: Fix LPC register offsets > pinctrl: aspeed-g5: Fix LPC register offsets > dt-bindings: aspeed-lpc: Remove LPC partitioning > > .../devicetree/bindings/mfd/aspeed-lpc.txt | 85 ++--------- > arch/arm/boot/dts/aspeed-g4.dtsi | 74 ++++------ > arch/arm/boot/dts/aspeed-g5.dtsi | 135 ++++++++---------- > arch/arm/boot/dts/aspeed-g6.dtsi | 135 ++++++++---------- > drivers/char/ipmi/kcs_bmc_aspeed.c | 13 +- > drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 2 +- > drivers/soc/aspeed/aspeed-lpc-ctrl.c | 6 +- > drivers/soc/aspeed/aspeed-lpc-snoop.c | 11 +- > 8 files changed, 176 insertions(+), 285 deletions(-) > > -- > 2.17.1