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Subject: Re: [PATCH v2 14/14] perf arm-spe: Add support for ARMv8.3-SPE
To:     Leo Yan <leo.yan@linaro.org>,
        Arnaldo Carvalho de Melo <acme@kernel.org>,
        Peter Zijlstra <peterz@infradead.org>,
        Ingo Molnar <mingo@redhat.com>,
        Mark Rutland <mark.rutland@arm.com>,
        Alexander Shishkin <alexander.shishkin@linux.intel.com>,
        Jiri Olsa <jolsa@redhat.com>,
        Namhyung Kim <namhyung@kernel.org>,
        Wei Li <liwei391@huawei.com>,
        James Clark <james.clark@arm.com>,
        Dave Martin <Dave.Martin@arm.com>,
        linux-kernel@vger.kernel.org, Al Grant <Al.Grant@arm.com>
References: <20200929133917.9224-1-leo.yan@linaro.org>
 <20200929133917.9224-15-leo.yan@linaro.org>
From:   =?UTF-8?Q?Andr=c3=a9_Przywara?= <andre.przywara@arm.com>
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Organization: ARM Ltd.
Message-ID: <9c74082b-fccf-7713-b98d-50da76c5d7af@arm.com>
Date:   Tue, 20 Oct 2020 22:54:44 +0100
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On 29/09/2020 14:39, Leo Yan wrote:

Hi,

> From: Wei Li <liwei391@huawei.com>
> 
> This patch is to support Armv8.3 extension for SPE, it adds alignment
> field in the Events packet and it supports the Scalable Vector Extension
> (SVE) for Operation packet and Events packet with two additions:
> 
>   - The vector length for SVE operations in the Operation Type packet;
>   - The incomplete predicate and empty predicate fields in the Events
>     packet.
> 
> Signed-off-by: Wei Li <liwei391@huawei.com>
> Signed-off-by: Leo Yan <leo.yan@linaro.org>
> ---
>  .../arm-spe-decoder/arm-spe-pkt-decoder.c     | 84 ++++++++++++++++++-
>  .../arm-spe-decoder/arm-spe-pkt-decoder.h     |  6 ++
>  2 files changed, 87 insertions(+), 3 deletions(-)
> 
> diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
> index 05a4c74399d7..3ec381fddfcb 100644
> --- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
> +++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
> @@ -342,14 +342,73 @@ int arm_spe_pkt_desc(const struct arm_spe_pkt *packet, char *buf,
>  					return ret;
>  			}
>  		}
> +		if (idx > 2) {

As I mentioned in the other patch, I doubt this extra comparison is
useful. Does that protect us from anything?

> +			if (payload & SPE_EVT_PKT_ALIGNMENT) {

Mmh, but this is bit 11, right? So would need to go into the (idx > 1)
section (covering bits 8-15)? Another reason to ditch this comparison above.

> +				ret = snprintf(buf, buf_len, " ALIGNMENT");
> +				if (ret < 0)
> +					return ret;
> +				buf += ret;
> +				blen -= ret;

Shouldn't we use the new arm_spe_pkt_snprintf() function here as well?
Or is there a reason that this doesn't work?

> +			}
> +			if (payload & SPE_EVT_PKT_SVE_PARTIAL_PREDICATE) {
> +				ret = snprintf(buf, buf_len, " SVE-PARTIAL-PRED");
> +				if (ret < 0)
> +					return ret;
> +				buf += ret;
> +				blen -= ret;
> +			}
> +			if (payload & SPE_EVT_PKT_SVE_EMPTY_PREDICATE) {
> +				ret = snprintf(buf, buf_len, " SVE-EMPTY-PRED");
> +				if (ret < 0)
> +					return ret;
> +				buf += ret;
> +				blen -= ret;
> +			}
> +		}
> +
>  		return buf_len - blen;
>  
>  	case ARM_SPE_OP_TYPE:
>  		switch (idx) {
>  		case SPE_OP_PKT_HDR_CLASS_OTHER:
> -			return arm_spe_pkt_snprintf(&buf, &blen,
> -					payload & SPE_OP_PKT_OTHER_SUBCLASS_COND ?
> -					"COND-SELECT" : "INSN-OTHER");
> +			if ((payload & SPE_OP_PKT_OTHER_SVE_SUBCLASS_MASK) ==
> +					SPE_OP_PKT_OTHER_SUBCLASS_SVG_OP) {
> +
> +				ret = arm_spe_pkt_snprintf(&buf, &blen, "SVE-OTHER");
> +				if (ret < 0)
> +					return ret;
> +
> +				/* Effective vector length: step is 32 bits */
> +				ret = arm_spe_pkt_snprintf(&buf, &blen, " EVLEN %d",
> +					32 << ((payload & SPE_OP_PKT_SVE_EVL_MASK) >>
> +						SPE_OP_PKT_SVE_EVL_SHIFT));

Can you move this into a macro, and add a comment about how this works?
People might get confused over the "32 << something".

Cheers,
Andre

> +				if (ret < 0)
> +					return ret;
> +
> +				if (payload & SPE_OP_PKT_SVE_FP) {
> +					ret = arm_spe_pkt_snprintf(&buf, &blen, " FP");
> +					if (ret < 0)
> +						return ret;
> +				}
> +				if (payload & SPE_OP_PKT_SVE_PRED) {
> +					ret = arm_spe_pkt_snprintf(&buf, &blen, " PRED");
> +					if (ret < 0)
> +						return ret;
> +				}
> +			} else {
> +				ret = arm_spe_pkt_snprintf(&buf, &blen, "OTHER");
> +				if (ret < 0)
> +					return ret;
> +
> +				ret = arm_spe_pkt_snprintf(&buf, &blen, " %s",
> +					       payload & SPE_OP_PKT_OTHER_SUBCLASS_COND ?
> +					       "COND-SELECT" : "UNCOND");
> +				if (ret < 0)
> +					return ret;
> +			}
> +
> +			return buf_len - blen;
> +
>  		case SPE_OP_PKT_HDR_CLASS_LD_ST_ATOMIC:
>  			ret = arm_spe_pkt_snprintf(&buf, &blen,
>  						   payload & SPE_OP_PKT_LDST ?
> @@ -394,6 +453,25 @@ int arm_spe_pkt_desc(const struct arm_spe_pkt *packet, char *buf,
>  				ret = arm_spe_pkt_snprintf(&buf, &blen, " NV-SYSREG");
>  				if (ret < 0)
>  					return ret;
> +			} else if ((payload & SPE_OP_PKT_LDST_SUBCLASS_SVE_MASK) ==
> +					SPE_OP_PKT_LDST_SUBCLASS_SVE) {
> +				/* Effective vector length: step is 32 bits */
> +				ret = arm_spe_pkt_snprintf(&buf, &blen, " EVLEN %d",
> +					32 << ((payload & SPE_OP_PKT_SVE_EVL_MASK) >>
> +						SPE_OP_PKT_SVE_EVL_SHIFT));
> +				if (ret < 0)
> +					return ret;
> +
> +				if (payload & SPE_OP_PKT_SVE_PRED) {
> +					ret = arm_spe_pkt_snprintf(&buf, &blen, " PRED");
> +					if (ret < 0)
> +						return ret;
> +				}
> +				if (payload & SPE_OP_PKT_SVE_SG) {
> +					ret = arm_spe_pkt_snprintf(&buf, &blen, " SG");
> +					if (ret < 0)
> +						return ret;
> +				}
>  			}
>  
>  			return buf_len - blen;
> diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
> index 1847cad517db..80266bfebec2 100644
> --- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
> +++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
> @@ -147,6 +147,12 @@ struct arm_spe_pkt {
>  #define SPE_OP_PKT_LDST_SUBCLASS_SVE_MASK	(GENMASK_ULL(3, 3) | GENMASK_ULL(1, 1))
>  #define SPE_OP_PKT_LDST_SUBCLASS_SVE		(0x8)
>  
> +#define SPE_OP_PKT_SVE_SG			BIT(7)
> +#define SPE_OP_PKT_SVE_EVL_MASK			GENMASK_ULL(6, 4)
> +#define SPE_OP_PKT_SVE_EVL_SHIFT		(4)
> +#define SPE_OP_PKT_SVE_PRED			BIT(2)
> +#define SPE_OP_PKT_SVE_FP			BIT(1)
> +
>  #define SPE_OP_PKT_AR				BIT(4)
>  #define SPE_OP_PKT_EXCL				BIT(3)
>  #define SPE_OP_PKT_AT				BIT(2)
>