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Wed, 21 Oct 2020 11:59:27 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp1.samsung.com (KnoxPortal) with ESMTP id 20201021115927eusmtrp1a5fd2918287d0dde791d195a4aeec1f7~AABc9yNuS3047130471eusmtrp1H; Wed, 21 Oct 2020 11:59:27 +0000 (GMT) X-AuditID: cbfec7f2-809ff70000001938-b2-5f90229f6a38 Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 00.BB.06314.E92209F5; Wed, 21 Oct 2020 12:59:26 +0100 (BST) Received: from [106.210.88.143] (unknown [106.210.88.143]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20201021115926eusmtip15186f6fcb609855a43f53997117081a1~AABb6V0BI2328223282eusmtip1S; Wed, 21 Oct 2020 11:59:25 +0000 (GMT) Subject: Re: [PATCH 2/6] Documetation: dt-bindings: add the samsung,exynos-pcie binding To: Krzysztof Kozlowski Cc: "linux-samsung-soc@vger.kernel.org" , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, "linux-kernel@vger.kernel.org" , Jaehoon Chung , Jingoo Han , Bjorn Helgaas , Lorenzo Pieralisi , Vinod Koul , Kishon Vijay Abraham I , Rob Herring From: Marek Szyprowski Message-ID: <50b13de0-168b-3fad-1e84-cc86f1a376d8@samsung.com> Date: Wed, 21 Oct 2020 13:59:25 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; 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charset="utf-8" X-RootMTR: 20201019094739eucas1p18cd4c7e5a0197393d2e7c5c6fcc2777d X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20201019094739eucas1p18cd4c7e5a0197393d2e7c5c6fcc2777d References: <20201019094715.15343-1-m.szyprowski@samsung.com> <20201019094715.15343-3-m.szyprowski@samsung.com> <20201019101233.GB51073@kozik-lap> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Krzysztof, On 19.10.2020 12:18, Krzysztof Kozlowski wrote: > On Mon, 19 Oct 2020 at 12:12, Krzysztof Kozlowski wrote: >> On Mon, Oct 19, 2020 at 11:47:11AM +0200, Marek Szyprowski wrote: >>> From: Jaehoon Chung >>> >>> Add dt-bindings for the Samsung Exynos PCIe controller (Exynos5433 >>> variant). >> The title has typo and actually entire "Doc" should be dropped. Just >> "dt-bindings: pci:". This applies to all DT patches. >> >>> Signed-off-by: Jaehoon Chung >>> [mszyprow: updated the binding to latest driver changes, rewrote it in yaml, >>> rewrote commit message] >> If you wrote them in YAML it should be a new patch of yours. It is the >> same then as converting TXT to YAML. >> >>> Signed-off-by: Marek Szyprowski >>> --- >>> .../bindings/pci/samsung,exynos-pcie.yaml | 106 ++++++++++++++++++ >>> 1 file changed, 106 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml >>> new file mode 100644 >>> index 000000000000..48fb569c238c >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml >>> @@ -0,0 +1,104 @@ >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>> +%YAML 1.2 >>> +--- >>> +$id: https://protect2.fireeye.com/v1/url?k=a6caf3f8-fb18e55d-a6cb78b7-0cc47a31bee8-bb3776dee0a03bbb&q=1&e=5f1b0c1e-e4d1-4ae2-b527-8cd5ec52695f&u=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fpci%2Fsamsung%2Cexynos-pcie.yaml%23 >>> +$schema: https://protect2.fireeye.com/v1/url?k=591573a2-04c76507-5914f8ed-0cc47a31bee8-bd08b2eac7a5040d&q=1&e=5f1b0c1e-e4d1-4ae2-b527-8cd5ec52695f&u=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23 >>> + >>> +title: Samsung SoC series PCIe Host Controller Device Tree Bindings >>> + >>> +maintainers: >>> + - Jaehoon Chung >>> + >>> +description: |+ >>> + Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare >>> + PCIe IP and thus inherits all the common properties defined in >>> + designware-pcie.txt. >>> + >>> +allOf: >>> + - $ref: /schemas/pci/pci-bus.yaml# >>> + >>> +properties: >>> + compatible: >>> + enum: >>> + - samsung,exynos5433-pcie >> const, not enum >> >>> + >>> + reg: >>> + items: >>> + - description: External Local Bus interface (ELBI) registers. >>> + - description: Data Bus Interface (DBI) registers. >>> + - description: PCIe configuration space region. >>> + >>> + reg-names: >>> + items: >>> + - const: elbi >>> + - const: bdi >>> + - const: config >>> + >>> + interrupts: >>> + maxItems: 1 >>> + >>> + clocks: >>> + items: >>> + - description: PCIe bridge clock >>> + - description: PCIe bus clock >>> + >>> + clock-names: >>> + items: >>> + - const: pcie >>> + - const: pcie_bus >>> + >>> + phys: >>> + maxItems: 1 >>> + >>> + phy-names: >>> + const: pcie-phy >>> + >>> + vdd10-supply: >>> + description: >>> + Phandle to a regulator that provides 1.0V power to the PCIe block. >>> + >>> + vdd18-supply: >>> + description: >>> + Phandle to a regulator that provides 1.8V power to the PCIe block. >>> + >>> +required: >>> + - reg >>> + - reg-names >>> + - interrupts >>> + - interrupt-names >>> + - clocks >>> + - clock-names >>> + - phys >>> + - phy-names >>> + - vdd10-supply >> additionalProperties: false > This can be unevaluatedProperties, since you include pci-bus schema. > However still you should either include designware schema or include > it's properties here. Frankly, I would like to include designware-pci bindling/schema, but it has not been converted to yaml yet. I don't feel that I know PCI enough to do that conversion... Best regards -- Marek Szyprowski, PhD Samsung R&D Institute Poland