Received: by 2002:a05:6a10:6744:0:0:0:0 with SMTP id w4csp5291027pxu; Wed, 21 Oct 2020 20:24:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzO1vaYO0imjIniL1q7jWIzQ8r+V+URtLg4GpNOEBC7GEyYW2BJOO6HwF6ovQyAdeRFgTZY X-Received: by 2002:a17:907:392:: with SMTP id ss18mr414275ejb.429.1603337086464; Wed, 21 Oct 2020 20:24:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1603337086; cv=none; d=google.com; s=arc-20160816; b=Q087xjZ4BwcLnrTEX6z51EeMnuP4otBCYD2l1zCuFtfkVNZiYPG90jOMFp7GeVmrlr 2jNDUKHTr9YG/G2Z49O/2QdB+9Ky4TVn3W8v/Nj9GpNydLFFwrkJqpwNXycs/gm/sh09 btgDlZpWxQB2oa4nWssZiOjvM7EB5fvQmhyRmq/ysgoKN1vF2WzLyLXxQ39B9QXenNo7 v9wAvItLGuC0lZbd8Ht8EldelPbhf0bNZC123/xeWAqz5GWfurO++WO+IkXX3jSOQMTr mSYaU2rqGluYt0N6HoJb5WNc0mX2s5qR7olq0Xpxluho/3hsLSHdiC5EZXHeuXn8VcJo HwBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:cc:to:from:date:dkim-signature; bh=TT/hPDcCjkJCenk8sLHU1Sek4T/MxX3FitCsX0otRRc=; b=YVO16uoujOEwF7C9l1oRnKcKg0+YWjV83sEibex6vLYXFo+CgqMdqjr/qH8W9CQaxw EjYzzJYM8hX6Q/B4rj3cN8Lr/KEvZoAyWwWZYqOJs339eYdvxaNHd+eR4FhfSb7HAU25 OI539R1eGZ3OBZZXI89TuAV8een9VBgwl2AiXBAS2SUpKCjkS2c5EKDYOTvHBRPqkBGP r7xy+iNSRenPzqGHZOe2/4GbBd1fwBwvzXZGw7E60ESO3p3pMs3FZLLqinyjXCP1EP/e VLYDTxJwd5QvmgWIkBWndoVGeIz7y42YUyydRNEY/HJNe7p1hrsLnz+zQ2bVCjEo6OII RPIQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tnlFBdD6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id p23si276746edw.241.2020.10.21.20.24.24; Wed, 21 Oct 2020 20:24:46 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tnlFBdD6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2443786AbgJUOzT (ORCPT + 99 others); Wed, 21 Oct 2020 10:55:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2443018AbgJUOzT (ORCPT ); Wed, 21 Oct 2020 10:55:19 -0400 Received: from mail-ed1-x541.google.com (mail-ed1-x541.google.com [IPv6:2a00:1450:4864:20::541]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 52B7DC0613CF for ; Wed, 21 Oct 2020 07:55:17 -0700 (PDT) Received: by mail-ed1-x541.google.com with SMTP id cq12so2911563edb.2 for ; Wed, 21 Oct 2020 07:55:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=TT/hPDcCjkJCenk8sLHU1Sek4T/MxX3FitCsX0otRRc=; b=tnlFBdD60NP1j8CKi3rq0v7z4WCacFdpguP+kTr9uz2MOzLrWy6v9UfR2aViCYoEs4 KNgexySZD6t48QEV0KYpCSCJQr1dAfmO5L3JY6/orVfiif1vNz6RTPCvO2z9suGyggQw ZP7CkNfToa3mHdlDo9xnCOF8GRwUleHlkUAmIJY9zZHgUqvebiMZjqJ95PTq4lJptC93 7btioFs3fVFwa26j3dBRkvE3qpbk/irVE/8cZeZbxswjcfy1LhRk2cTmiwobkzVVMqki nhvW//0XltzV4dYBqGiG2MrKzCNIfn0BDtzQ4Z1etG4sws1lKittG2ZNKnfwqBjJhYBx izcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=TT/hPDcCjkJCenk8sLHU1Sek4T/MxX3FitCsX0otRRc=; b=QUxlkZRfBRkanWQXkZ/ik9gO3USjQq+uaSq5pzTYusFBDEuOA46eBRpWhe4PTHcJBk p0KAM9ttVOjZ5QfpFFmQCatMYE/WKPdeF2AKgO68jY6XWh4/cxsWrNg8pr2HxrTwA2Fr fEcfZ/7Fk/uR15s+S0yFCYN/H0U9Ep2UgLpM9t0yvLlHjo7c6iVV60kiY1umw0kHWUoI ruUWtZZo0ttuUdxypNWH0JApUA7p6kgWR9cB4chGT7V+GKtDSgz7XSgDMhCfxQ6Lk3wh 8qib6iumTLsRT0EaWzHfqAHyL9zDG1NaA6LKGCrBwJNv15ZRNksd6LEMRQZLJq2rb7Qi JGtA== X-Gm-Message-State: AOAM532A3FoFlnEK1190OlcFbYamcxRkTJ+CBmX5bpuyqKxl2R2tAai4 rU0JQaEnPM+cySaXT2MylR82uw== X-Received: by 2002:a50:8acf:: with SMTP id k15mr3413516edk.351.1603292116012; Wed, 21 Oct 2020 07:55:16 -0700 (PDT) Received: from myrica ([2001:1715:4e26:a7e0:116c:c27a:3e7f:5eaf]) by smtp.gmail.com with ESMTPSA id lb11sm2406579ejb.27.2020.10.21.07.55.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Oct 2020 07:55:15 -0700 (PDT) Date: Wed, 21 Oct 2020 16:54:56 +0200 From: Jean-Philippe Brucker To: Jacob Pan Cc: iommu@lists.linux-foundation.org, LKML , Joerg Roedel , Alex Williamson , Lu Baolu , David Woodhouse , Jonathan Corbet , linux-api@vger.kernel.org, Jean-Philippe Brucker , Eric Auger , Jacob Pan , Yi Liu , "Tian, Kevin" , Raj Ashok , Wu Hao , Yi Sun , Dave Jiang , Randy Dunlap Subject: Re: [PATCH v3 04/14] iommu/ioasid: Support setting system-wide capacity Message-ID: <20201021145456.GB1653231@myrica> References: <1601329121-36979-1-git-send-email-jacob.jun.pan@linux.intel.com> <1601329121-36979-5-git-send-email-jacob.jun.pan@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1601329121-36979-5-git-send-email-jacob.jun.pan@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Sep 28, 2020 at 02:38:31PM -0700, Jacob Pan wrote: > IOASID is a system-wide resource that could vary on different systems. > The default capacity is 20 bits as defined in the PCI-E specifications. > This patch adds a function to allow adjusting system IOASID capacity. > For VT-d this is set during boot as part of the Intel IOMMU > initialization. > > Signed-off-by: Jacob Pan Reviewed-by: Jean-Philippe Brucker > --- > drivers/iommu/intel/iommu.c | 5 +++++ > drivers/iommu/ioasid.c | 20 ++++++++++++++++++++ > include/linux/ioasid.h | 11 +++++++++++ > 3 files changed, 36 insertions(+) > > diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c > index 18ed3b3c70d7..e7bcb299e51e 100644 > --- a/drivers/iommu/intel/iommu.c > +++ b/drivers/iommu/intel/iommu.c > @@ -42,6 +42,7 @@ > #include > #include > #include > +#include (not in alphabetical order) > #include > #include > #include > @@ -3331,6 +3332,10 @@ static int __init init_dmars(void) > if (ret) > goto free_iommu; > > + /* PASID is needed for scalable mode irrespective to SVM */ > + if (intel_iommu_sm) > + ioasid_install_capacity(intel_pasid_max_id); > + > /* > * for each drhd > * enable fault log > diff --git a/drivers/iommu/ioasid.c b/drivers/iommu/ioasid.c > index 6cfbdfb492e0..4277cb17e15b 100644 > --- a/drivers/iommu/ioasid.c > +++ b/drivers/iommu/ioasid.c > @@ -10,6 +10,10 @@ > #include > #include > > +/* Default to PCIe standard 20 bit PASID */ > +#define PCI_PASID_MAX 0x100000 > +static ioasid_t ioasid_capacity = PCI_PASID_MAX; > +static ioasid_t ioasid_capacity_avail = PCI_PASID_MAX; > struct ioasid_data { > ioasid_t id; > struct ioasid_set *set; > @@ -17,6 +21,22 @@ struct ioasid_data { > struct rcu_head rcu; > }; > > +void ioasid_install_capacity(ioasid_t total) > +{ > + if (ioasid_capacity && ioasid_capacity != PCI_PASID_MAX) { > + pr_warn("IOASID capacity is already set.\n"); > + return; > + } > + ioasid_capacity = ioasid_capacity_avail = total; > +} > +EXPORT_SYMBOL_GPL(ioasid_install_capacity); > + > +ioasid_t ioasid_get_capacity(void) > +{ > + return ioasid_capacity; > +} > +EXPORT_SYMBOL_GPL(ioasid_get_capacity); > + > /* > * struct ioasid_allocator_data - Internal data structure to hold information > * about an allocator. There are two types of allocators: > diff --git a/include/linux/ioasid.h b/include/linux/ioasid.h > index c7f649fa970a..7fc320656be2 100644 > --- a/include/linux/ioasid.h > +++ b/include/linux/ioasid.h > @@ -32,6 +32,8 @@ struct ioasid_allocator_ops { > #define DECLARE_IOASID_SET(name) struct ioasid_set name = { 0 } > > #if IS_ENABLED(CONFIG_IOASID) > +void ioasid_install_capacity(ioasid_t total); > +ioasid_t ioasid_get_capacity(void); > ioasid_t ioasid_alloc(struct ioasid_set *set, ioasid_t min, ioasid_t max, > void *private); > void ioasid_free(ioasid_t ioasid); > @@ -42,6 +44,15 @@ void ioasid_unregister_allocator(struct ioasid_allocator_ops *allocator); > int ioasid_attach_data(ioasid_t ioasid, void *data); > void ioasid_detach_data(ioasid_t ioasid); > #else /* !CONFIG_IOASID */ > +static inline void ioasid_install_capacity(ioasid_t total) > +{ > +} > + > +static inline ioasid_t ioasid_get_capacity(void) > +{ > + return 0; > +} > + > static inline ioasid_t ioasid_alloc(struct ioasid_set *set, ioasid_t min, > ioasid_t max, void *private) > { > -- > 2.7.4 >