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From:   Fabien Parent <fparent@baylibre.com>
Date:   Wed, 21 Oct 2020 20:56:32 +0200
Message-ID: <CAOwMV_wvf6v1acXjtuB3Sm83YNyf=A7ULJkEDz7RY7T7mijqHg@mail.gmail.com>
Subject: Re: [PATCH 2/8] dt-bindings: display: mediatek: dsi: add
 documentation for MT8167 SoC
To:     Chun-Kuang Hu <chunkuang.hu@kernel.org>
Cc:     "moderated list:ARM/Mediatek SoC support" 
        <linux-mediatek@lists.infradead.org>,
        Linux ARM <linux-arm-kernel@lists.infradead.org>,
        linux-kernel <linux-kernel@vger.kernel.org>,
        DTML <devicetree@vger.kernel.org>,
        DRI Development <dri-devel@lists.freedesktop.org>,
        Matthias Brugger <matthias.bgg@gmail.com>,
        Rob Herring <robh+dt@kernel.org>,
        Daniel Vetter <daniel@ffwll.ch>,
        David Airlie <airlied@linux.ie>,
        Philipp Zabel <p.zabel@pengutronix.de>
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Hi Chun-Kuang,

On Wed, Oct 21, 2020 at 7:01 PM Chun-Kuang Hu <chunkuang.hu@kernel.org> wro=
te:
>
> Hi, Fabien:
>
> Fabien Parent <fparent@baylibre.com> =E6=96=BC 2020=E5=B9=B410=E6=9C=8821=
=E6=97=A5 =E9=80=B1=E4=B8=89 =E4=B8=8A=E5=8D=881:43=E5=AF=AB=E9=81=93=EF=BC=
=9A
> >
> > Add binding documentation for the MT8167 SoC. The SoC needs
> > an additional clock compared to the already supported SoC: mipi26m.
> >
> > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> > ---
> >  .../devicetree/bindings/display/mediatek/mediatek,dsi.txt  | 7 ++++---
> >  1 file changed, 4 insertions(+), 3 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediate=
k,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi=
.txt
> > index f06f24d405a5..10ae6be7225e 100644
> > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.t=
xt
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.t=
xt
> > @@ -7,12 +7,13 @@ channel output.
> >
> >  Required properties:
> >  - compatible: "mediatek,<chip>-dsi"
> > -- the supported chips are mt2701, mt7623, mt8173 and mt8183.
> > +- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
> >  - reg: Physical base address and length of the controller's registers
> >  - interrupts: The interrupt signal from the function block.
> >  - clocks: device clocks
> >    See Documentation/devicetree/bindings/clock/clock-bindings.txt for d=
etails.
> > -- clock-names: must contain "engine", "digital", and "hs"
> > +- clock-names: must contain "engine", "digital", "hs"
> > +  Can optionnally also contain "mipi26m"
>
> It seems that mipi26m is the clock of mipi-tx. In mt8173.dtsi [1],
> mipi-tx's clock is 26m.
>
> mipi_tx0: mipi-dphy@10215000 {
> compatible =3D "mediatek,mt8173-mipi-tx";
> reg =3D <0 0x10215000 0 0x1000>;
> clocks =3D <&clk26m>;
> clock-output-names =3D "mipi_tx0_pll";
> #clock-cells =3D <0>;
> #phy-cells =3D <0>;
> status =3D "disabled";
> };
>
> If this is the clock of mipi-tx, it should be controlled by mipi-tx drive=
r.

Thanks, I will fix that in v2.

>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tr=
ee/arch/arm64/boot/dts/mediatek/mt8173.dtsi?h=3Dv5.9
>
> Regards,
> Chun-Kuang.
>
> >  - phys: phandle link to the MIPI D-PHY controller.
> >  - phy-names: must contain "dphy"
> >  - port: Output port node with endpoint definitions as described in
> > @@ -26,7 +27,7 @@ The MIPI TX configuration module controls the MIPI D-=
PHY.
> >
> >  Required properties:
> >  - compatible: "mediatek,<chip>-mipi-tx"
> > -- the supported chips are mt2701, 7623, mt8173 and mt8183.
> > +- the supported chips are mt2701, 7623, mt8167, mt8173 and mt8183.
> >  - reg: Physical base address and length of the controller's registers
> >  - clocks: PLL reference clock
> >  - clock-output-names: name of the output clock line to the DSI encoder
> > --
> > 2.28.0
> >