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Subject: Re: [PATCH v1 6/6] i2c: iproc: handle rx fifo full interrupt
To:     Dhananjay Phadke <dphadke@linux.microsoft.com>,
        rayagonda.kokatanur@broadcom.com
Cc:     andriy.shevchenko@linux.intel.com,
        bcm-kernel-feedback-list@broadcom.com, brendanhiggins@google.com,
        f.fainelli@gmail.com, linux-arm-kernel@lists.infradead.org,
        linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org,
        lori.hikichi@broadcom.com, rjui@broadcom.com,
        sbranden@broadcom.com, wsa@kernel.org
References: <20201011182254.17776-7-rayagonda.kokatanur@broadcom.com>
 <20201011182254.17776-7-rayagonda.kokatanur@broadcom.com>
From:   Ray Jui <ray.jui@broadcom.com>
Message-ID: <e9d15e5a-e868-baff-177f-81aa1d742ff1@broadcom.com>
Date:   Fri, 23 Oct 2020 10:42:04 -0700
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On 10/12/2020 3:03 PM, Dhananjay Phadke wrote:
> From: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
> 
> On Sun, 11 Oct 2020 23:52:54 +0530, Rayagonda Kokatanur wrote:
>> Add code to handle IS_S_RX_FIFO_FULL_SHIFT interrupt to support
>> master write request with >= 64 bytes.
>>
>> Iproc has a slave rx fifo size of 64 bytes.
>> Rx fifo full interrupt (IS_S_RX_FIFO_FULL_SHIFT) will be generated
>> when RX fifo becomes full. This can happen if master issues write
>> request of more than 64 bytes.
>>
> 
> ARM cores run much faster than I2C bus, why would rx fifo go full when
> rx interrupt is enabled and bytes are read out by bus driver isr?
> Isn't fifo read pointer updated on these byte reads?

Hi Rayagonda,

Could you please reply on this question? For transactions > 64 bytes, do
we batch until RX FIFO is full before we read out the data?

Thanks,

Ray

> Does controller stretch clock when rx fifo is full (e.g. kernel has
> crashed, bus driver isn't draining fifo)?
> 

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