Received: by 2002:a05:6a10:6744:0:0:0:0 with SMTP id w4csp903609pxu; Fri, 23 Oct 2020 16:52:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwKhUt9yGBFekOCEKoYv/GcaJ54F6mikh25sXjlA3S6gHwARoc249FL0xCJIP4bJufUq7ri X-Received: by 2002:a17:906:280a:: with SMTP id r10mr2653085ejc.45.1603497168594; Fri, 23 Oct 2020 16:52:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1603497168; cv=none; d=google.com; s=arc-20160816; b=kNdiKdr0ITrW6eg3tljnkLHzAwK3tTWPBJiUZpKAOxTHhhe4p37uXcRctqMSh+nXrS WTkcox3fkT97fC578K9p3R3+MLUdjzEc/7Sa9Rrv7mLC2FEVUYN0TAj6L2w4QvGvs3WU toLVrAXkYbZ3UCwmTa6k1uYTBuneXv8hKpalJGR10sbLXjVcko7LOg6idXjMCgqNC5fG jIU9SKJ0IvgjKJ4k9ZZVX7RJyesjlDWCqgGLl/IIgBC4bSILSTMtCpg3GHqBiwhOQIJG b4L4SBTRdPe80stjbzc8+nxKWj7kQifKU/zjSYzlEGK3cdFHOlz9Zx8Qwc75pvYfJ90J tiiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:dkim-signature:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from; bh=Lcu11GtGa94b8F15yYcftGZjf+99kinzBPZEJ0Hk4Nc=; b=i70y0asYbGqt9gXQoGJrg5R/cvCZo+VCZ894UHhR81i+Cng7BK5YGabo9hePveUAr0 3QunpowSE3n9qgEct0+xRYax4vpRdEpZuywR4KKDYH3YhHRsQ1wWsT1DNpuAzGWNp68z ewmbjisfbDSXrFs69clSuhQr6ovAMQECAzDV/B0+Q3sx2Rmv7GcPuVuQOiaLkrT2BaMB 5qgqK/i+v18WBx+XDLMAqF91z+g4zlnuS7F5cXc5zYlbCnjanHQhoubO9jtojFaz54UF AmElyVKv6bMx1sDu0ay8EOgjKvke3EN6ZM2XUTukqg6F3P3WsFNE7ZQTEk8GvqTwQuHu tfLg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=S6afGSdJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id c18si1913644eja.521.2020.10.23.16.52.25; Fri, 23 Oct 2020 16:52:48 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=S6afGSdJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755242AbgJWT5Q (ORCPT + 99 others); Fri, 23 Oct 2020 15:57:16 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:17019 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755237AbgJWT5P (ORCPT ); Fri, 23 Oct 2020 15:57:15 -0400 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Fri, 23 Oct 2020 12:56:55 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 23 Oct 2020 19:57:14 +0000 Received: from vidyas-desktop.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Fri, 23 Oct 2020 19:57:09 +0000 From: Vidya Sagar To: , , , , , , , CC: , , , , , Subject: [PATCH 2/3] PCI: dwc: Add support to program ATU for >4GB memory aperture sizes Date: Sat, 24 Oct 2020 01:26:54 +0530 Message-ID: <20201023195655.11242-3-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201023195655.11242-1-vidyas@nvidia.com> References: <20201023195655.11242-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1603483015; bh=Lcu11GtGa94b8F15yYcftGZjf+99kinzBPZEJ0Hk4Nc=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=S6afGSdJjwBWM4IYoOg6hqyhHO1q+IAH0Qmj+4FXMNQhCp87Rf8E5jKNYPautjK82 J3fO7M6lYltynXhUkhQ5V9sl9TfStISjSnaS6MEd0fH5yW1xxxJrzKsNsibfDUozl8 gKUxAlVHarA0u8V8UUqDgRtFL13w10JM8YzhvzKL6MxGQhfU5Oppplu4Pwapv4BrmN hxX0y8sxa8Nz1tEC76d4y9W03zsM38+ReY25ijlE4bD7Az7AxW0g+VEh4nLdSFmCWp lfaJvC6lIslRJ5RIM2/DAszdTtB2J6OvcgLxiT1O4v5k1a6OLUpCyxAnAgov7tCETn ExpAMNY0s30Sg== Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support to program the ATU to enable translations for >4GB sizes of the prefetchable memory apertures. Signed-off-by: Vidya Sagar --- drivers/pci/controller/dwc/pcie-designware.c | 12 +++++++----- drivers/pci/controller/dwc/pcie-designware.h | 3 ++- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index c2dea8fc97c8..b5e438b70cd5 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -228,7 +228,7 @@ static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg, static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, u8 func_no, int index, int type, u64 cpu_addr, u64 pci_addr, - u32 size) + u64 size) { u32 retries, val; u64 limit_addr = cpu_addr + size - 1; @@ -245,8 +245,10 @@ static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, u8 func_no, lower_32_bits(pci_addr)); dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, upper_32_bits(pci_addr)); - dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, - type | PCIE_ATU_FUNC_NUM(func_no)); + val = type | PCIE_ATU_FUNC_NUM(func_no); + val = upper_32_bits(size - 1) ? + val | PCIE_ATU_INCREASE_REGION_SIZE : val; + dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, val); dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, PCIE_ATU_ENABLE); @@ -267,7 +269,7 @@ static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, u8 func_no, static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, int index, int type, u64 cpu_addr, - u64 pci_addr, u32 size) + u64 pci_addr, u64 size) { u32 retries, val; @@ -311,7 +313,7 @@ static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, } void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, - u64 cpu_addr, u64 pci_addr, u32 size) + u64 cpu_addr, u64 pci_addr, u64 size) { __dw_pcie_prog_outbound_atu(pci, 0, index, type, cpu_addr, pci_addr, size); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 9d2f511f13fa..e7f441441db2 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -84,6 +84,7 @@ #define PCIE_ATU_REGION_INDEX1 0x1 #define PCIE_ATU_REGION_INDEX0 0x0 #define PCIE_ATU_CR1 0x904 +#define PCIE_ATU_INCREASE_REGION_SIZE BIT(13) #define PCIE_ATU_TYPE_MEM 0x0 #define PCIE_ATU_TYPE_IO 0x2 #define PCIE_ATU_TYPE_CFG0 0x4 @@ -295,7 +296,7 @@ void dw_pcie_upconfig_setup(struct dw_pcie *pci); int dw_pcie_wait_for_link(struct dw_pcie *pci); void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, u64 cpu_addr, u64 pci_addr, - u32 size); + u64 size); void dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index, int type, u64 cpu_addr, u64 pci_addr, u32 size); -- 2.17.1