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From:   Leo Li <leoyang.li@nxp.com>
To:     Marc Zyngier <maz@kernel.org>,
        Rasmus Villemoes <linux@rasmusvillemoes.dk>
CC:     "Biwen Li (OSS)" <biwen.li@oss.nxp.com>,
        "shawnguo@kernel.org" <shawnguo@kernel.org>,
        "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "mark.rutland@arm.com" <mark.rutland@arm.com>,
        "Z.q. Hou" <zhiqiang.hou@nxp.com>,
        "tglx@linutronix.de" <tglx@linutronix.de>,
        "jason@lakedaemon.net" <jason@lakedaemon.net>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Jiafei Pan <jiafei.pan@nxp.com>,
        Xiaobo Xie <xiaobo.xie@nxp.com>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>, Biwen Li <biwen.li@nxp.com>
Subject: RE: [RESEND 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A external
 interrupt
Thread-Topic: [RESEND 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A external
 interrupt
Thread-Index: AQHWq2+CLg8O51zq50exYYqsZaIXIKmpkXkAgAAGWgCAAARoAIAAW4Tg
Date:   Mon, 26 Oct 2020 15:06:19 +0000
Message-ID: <VE1PR04MB668737DF1DDA6E1007BCA24C8F190@VE1PR04MB6687.eurprd04.prod.outlook.com>
References: <20201026080127.40499-1-biwen.li@oss.nxp.com>
 <31d8971374c261003aee9f4807c8ac8c@kernel.org>
 <3448c822-31b1-7f9d-fedf-49912418fc3f@rasmusvillemoes.dk>
 <b65acafab54b62a2a22aa942089b8033@kernel.org>
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> -----Original Message-----
> From: Marc Zyngier <maz@kernel.org>
> Sent: Monday, October 26, 2020 4:23 AM
> To: Rasmus Villemoes <linux@rasmusvillemoes.dk>
> Cc: Biwen Li (OSS) <biwen.li@oss.nxp.com>; shawnguo@kernel.org;
> robh+dt@kernel.org; mark.rutland@arm.com; Leo Li <leoyang.li@nxp.com>;
> Z.q. Hou <zhiqiang.hou@nxp.com>; tglx@linutronix.de;
> jason@lakedaemon.net; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; Jiafei Pan <jiafei.pan@nxp.com>; Xiaobo Xie
> <xiaobo.xie@nxp.com>; linux-arm-kernel@lists.infradead.org; Biwen Li
> <biwen.li@nxp.com>
> Subject: Re: [RESEND 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A exte=
rnal
> interrupt
>=20
> On 2020-10-26 09:06, Rasmus Villemoes wrote:
> > On 26/10/2020 09.44, Marc Zyngier wrote:
> >> On 2020-10-26 08:01, Biwen Li wrote:
> >>> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >>>
> >>> Add an new IRQ chip declaration for LS1043A and LS1088A
> >>> - compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A
> >>> - compatible "fsl,ls1088a-extirq" for LS1088A, LS208xA, LX216xA
> >>
> >> Three things:
> >> - This commit message doesn't describe the bit_reverse change
> >
> > Yeah, please elaborate on that, as the RM for 1043 or 1046 doesn't
> > mention anything about bit reversal for the scfg registers - they
> > don't seem to have the utter nonsense that is SCFG_SCFGREVCR, but
> > perhaps, instead of removing it, that has just become a hard-coded
> > part of the IP.
> >
> > Also, IANAL etc., but
> >
> >>> +// Copyright 2019-2020 NXP
> >
> > really? Seems to be a bit of a stretch.
> >
> > At the very least, cc'ing the original author and only person to ever
> > touch that file would have been appreciated.
>=20
> Huh. Well spotted. That's definitely not on.
> NXP people, please talk to your legal department.

We do have an internal policy to require developer adding/updating NXP copy=
right on non-trivial changes.  I'm not sure if this change should be consid=
ered trivial, but adding copyright claim on a file without prior copyright =
claims could causing confusion like in this case.  One potential solution i=
s to add a more specific description on the NXP change together with the co=
pyright claim.  But maybe an easier solution is to add Rasmus your Copyrigh=
t claim first if you are ok with it.

Regards,
Leo