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Date:   Mon, 26 Oct 2020 21:17:58 +0100
From:   Krzysztof Kozlowski <krzk@kernel.org>
To:     Nicolin Chen <nicoleotsuka@gmail.com>
Cc:     Thierry Reding <thierry.reding@gmail.com>, robh+dt@kernel.org,
        jonathanh@nvidia.com, linux-tegra@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 4/5] dt-bindings: memory: tegra: Add missing swgroups
Message-ID: <20201026201758.GD248919@kozik-lap>
References: <20201008003746.25659-1-nicoleotsuka@gmail.com>
 <20201008003746.25659-5-nicoleotsuka@gmail.com>
 <20201009122110.GD458338@ulmo>
 <20201009155218.GA4469@Asurada-Nvidia>
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In-Reply-To: <20201009155218.GA4469@Asurada-Nvidia>
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On Fri, Oct 09, 2020 at 08:52:18AM -0700, Nicolin Chen wrote:
> On Fri, Oct 09, 2020 at 02:21:10PM +0200, Thierry Reding wrote:
> > On Wed, Oct 07, 2020 at 05:37:45PM -0700, Nicolin Chen wrote:
> > > According to Tegra X1 TRM, there are missing swgroups in the
> > > tegra210_swgroups list. So this patch adds them in bindings.
> > > 
> > > Note that the TEGRA_SWGROUP_GPU (in list) should be actually
> > > TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM)
> > > is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So
> > > this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps
> > > TEGRA_SWGROUP_GPU (in list) as it is.
> > > 
> > > Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> > > ---
> > >  include/dt-bindings/memory/tegra210-mc.h | 10 ++++++++++
> > >  1 file changed, 10 insertions(+)
> > > 
> > > diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h
> > > index c226cba9e077..f9fcb18a6d9b 100644
> > > --- a/include/dt-bindings/memory/tegra210-mc.h
> > > +++ b/include/dt-bindings/memory/tegra210-mc.h
> > > @@ -33,6 +33,16 @@
> > >  #define TEGRA_SWGROUP_AXIAP	28
> > >  #define TEGRA_SWGROUP_ETR	29
> > >  #define TEGRA_SWGROUP_TSECB	30
> > > +#define TEGRA_SWGROUP_NV	31
> > > +#define TEGRA_SWGROUP_NV2	32
> > > +#define TEGRA_SWGROUP_PPCS1	33
> > > +#define TEGRA_SWGROUP_DC1	34
> > > +#define TEGRA_SWGROUP_PPCS2	35
> > > +#define TEGRA_SWGROUP_HC1	36
> > > +#define TEGRA_SWGROUP_SE1	37
> > > +#define TEGRA_SWGROUP_TSEC1	38
> > > +#define TEGRA_SWGROUP_TSECB1	39
> > > +#define TEGRA_SWGROUP_NVDEC1	40
> > 
> > I'm not sure this is right. The existing list is based on "Table 4:
> > Client to Software Name Mapping" from page 28 of the Tegra X1 TRM, and
> > none of these new swgroups seem to be present in that table.
> 
> I went through all the MC_SMMU_XX_ASID_0 registers. All of
> them have their own ASID registers that I added in PATCH-5.

Thierry,

Any follow ups on this topic? Does it require a fix or looks correct?

Best regards,
Krzysztof