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[23.128.96.18]) by mx.google.com with ESMTP id 11si1464507ejv.311.2020.10.27.10.53.25; Tue, 27 Oct 2020 10:53:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kylehuey.com header.s=google header.b=i9YMhQXS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1818664AbgJ0RWu (ORCPT + 99 others); Tue, 27 Oct 2020 13:22:50 -0400 Received: from mail-ej1-f66.google.com ([209.85.218.66]:46251 "EHLO mail-ej1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1811816AbgJ0RWs (ORCPT ); Tue, 27 Oct 2020 13:22:48 -0400 Received: by mail-ej1-f66.google.com with SMTP id t25so3330722ejd.13 for ; Tue, 27 Oct 2020 10:22:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kylehuey.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=X2/9Hit5668ey8vyUaaKLnC7mcM4OnkN5mepGXepYuc=; b=i9YMhQXS6mpLeHIjUr6MJln8eCraOodhXeykTEkJPevVHjU/Ps46wH/1SjHPDX8HZ9 I4iz6MLgNAiZC1HJSEqvcXYGPvm6chRqamv45o0yDLZLS5CBsMs3xPtKVRClH2NA+5LV TS3GkOIEqghaV9L7Io9X1qlXm2tysuSSkTQwMWWGhthx5mk8PA54i9w1ZWqe+2vIcHkX /u5A4oAD5VLk4PzcMLCdl+Nfmwqvbw4rA2KlZCNmzV/HMhZvI43rw/PQ7xhTOe/LLRx/ N/13WvQSPI42px8YdPiFbMHs1xQHFZdT1RTUZKZB4pkly/02LiWON5Dr+TE7YeM1sZYx Ybag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=X2/9Hit5668ey8vyUaaKLnC7mcM4OnkN5mepGXepYuc=; b=h/05lJ/IopQaCHWaMvVVDO6qPEJ89ZbmUUuxo8+m3TU/pniZnIP2OGuJ79XTBmqWGI QGYRukfk8vs0HAaa4YoOHxNOSiTPcsbjQ78pdyAg9Np31xn7BIDTSmvM2mVSzJ44a8+C AyCONmYM8xba6PMuSNdkDpGkFEYwdJrkofANNzarN1OoXvYMtKjvzOJavfpuqOvg0zvl xX/PjGyUJrMbVOJNAha5Ku3K2DxwDmnEc5ZgoTIhoLGqbVgfl/bOKjA6birup92lCxEi Twu2G6fHRRqyfxxhV1YLpRYOcqB1d3XUjkdD22wGV31kwmsxbRW/YZGUtVGj2cHTUC2a wNzQ== X-Gm-Message-State: AOAM530s/eMPVNphtv5mGo0EcTfzP5qjQzck256GhTxWgEnjTzqtWYPq 6lSm3Ku0ta3z5LOKhqmY+vFmzEwCF1/cC+Dzpg3oVw== X-Received: by 2002:a17:906:b285:: with SMTP id q5mr3570859ejz.135.1603819365979; Tue, 27 Oct 2020 10:22:45 -0700 (PDT) MIME-Version: 1.0 References: <20201027091504.712183781@infradead.org> <20201027093608.096535386@infradead.org> In-Reply-To: <20201027093608.096535386@infradead.org> From: Kyle Huey Date: Tue, 27 Oct 2020 10:22:34 -0700 Message-ID: Subject: Re: [PATCH 3/3] x86/debug: Fix PTRACE_{BLOCK,SINGLE}STEP vs ptrace_get_debugreg(6) To: Peter Zijlstra Cc: Thomas Gleixner , Andy Lutomirski , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , open list , Linus Torvalds , "Robert O'Callahan" , Alexandre Chartre , "Paul E. McKenney" , Frederic Weisbecker , Paolo Bonzini , Sean Christopherson , Masami Hiramatsu , Petr Mladek , Joel Fernandes , Steven Rostedt , Boris Ostrovsky , Juergen Gross , Brian Gerst , Josh Poimboeuf , Daniel Thompson , julliard@winehq.org, pgofman@codeweavers.com Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Oct 27, 2020 at 2:44 AM Peter Zijlstra wrote: > > Commit d53d9bc0cf78 ("x86/debug: Change thread.debugreg6 to > thread.virtual_dr6") changed the semantics of the variable from random > collection of bits, to exactly only those bits that ptrace() needs. > > Unfortunately we lost DR_STEP for PTRACE_{BLOCK,SINGLE}STEP. > > Fixes: d53d9bc0cf78 ("x86/debug: Change thread.debugreg6 to thread.virtual_dr6") > Reported-by: Kyle Huey > Signed-off-by: Peter Zijlstra (Intel) > --- > arch/x86/include/asm/ptrace.h | 2 ++ > arch/x86/kernel/step.c | 9 +++++++++ > arch/x86/kernel/traps.c | 2 +- > 3 files changed, 12 insertions(+), 1 deletion(-) > > --- a/arch/x86/include/asm/ptrace.h > +++ b/arch/x86/include/asm/ptrace.h > @@ -355,6 +355,8 @@ static inline unsigned long regs_get_ker > #define arch_has_block_step() (boot_cpu_data.x86 >= 6) > #endif > > +extern unsigned long user_dr_step(unsigned long dr6); > + > #define ARCH_HAS_USER_SINGLE_STEP_REPORT > > struct user_desc; > --- a/arch/x86/kernel/step.c > +++ b/arch/x86/kernel/step.c > @@ -235,3 +235,12 @@ void user_disable_single_step(struct tas > if (test_and_clear_tsk_thread_flag(child, TIF_FORCED_TF)) > task_pt_regs(child)->flags &= ~X86_EFLAGS_TF; > } > + > +unsigned long user_dr_step(unsigned long dr6) > +{ > + if (test_thread_flag(TIF_BLOCKSTEP) || > + test_thread_flag(TIF_SINGLESTEP)) > + return dr6 & DR_STEP; > + > + return 0; > +} > --- a/arch/x86/kernel/traps.c > +++ b/arch/x86/kernel/traps.c > @@ -940,7 +940,7 @@ static __always_inline void exc_debug_us > * Clear the virtual DR6 value, ptrace() routines will set bits here > * for things it wants signals for. > */ > - current->thread.virtual_dr6 = 0; > + current->thread.virtual_dr6 = user_dr_step(dr6); > > /* > * The SDM says "The processor clears the BTF flag when it > > Tested-by: Kyle Huey Confirmed that this patch series fixes rr when applied on top of the v5.10-rc1 tag. - Kyle