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From:   "Biwen Li (OSS)" <biwen.li@oss.nxp.com>
To:     Rasmus Villemoes <linux@rasmusvillemoes.dk>,
        Marc Zyngier <maz@kernel.org>,
        "Biwen Li (OSS)" <biwen.li@oss.nxp.com>
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        Leo Li <leoyang.li@nxp.com>, "Z.q. Hou" <zhiqiang.hou@nxp.com>,
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        Xiaobo Xie <xiaobo.xie@nxp.com>,
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        <linux-arm-kernel@lists.infradead.org>
Subject: RE: [RESEND 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A external
 interrupt
Thread-Topic: [RESEND 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A external
 interrupt
Thread-Index: AQHWrBDg23J7/+yWj0uXRQhWZKYN/w==
Date:   Tue, 27 Oct 2020 03:25:53 +0000
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References: <20201026080127.40499-1-biwen.li@oss.nxp.com>
 <31d8971374c261003aee9f4807c8ac8c@kernel.org>
 <3448c822-31b1-7f9d-fedf-49912418fc3f@rasmusvillemoes.dk>
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> Subject: Re: [RESEND 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A exte=
rnal
> interrupt
>=20
> On 26/10/2020 09.44, Marc Zyngier wrote:
> > On 2020-10-26 08:01, Biwen Li wrote:
> >> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >>
> >> Add an new IRQ chip declaration for LS1043A and LS1088A
> >> - compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A
> >> - compatible "fsl,ls1088a-extirq" for LS1088A, LS208xA, LX216xA
> >
> > Three things:
> > - This commit message doesn't describe the bit_reverse change
>=20
> Yeah, please elaborate on that, as the RM for 1043 or 1046 doesn't mentio=
n
> anything about bit reversal for the scfg registers - they don't seem to h=
ave the
> utter nonsense that is SCFG_SCFGREVCR, but perhaps, instead of removing i=
t,
> that has just become a hard-coded part of the IP.
Yeah, you are right, I will update it in v2.
>=20
> Also, IANAL etc., but
>=20
> >> +// Copyright 2019-2020 NXP
>=20
> really? Seems to be a bit of a stretch.
>=20
> At the very least, cc'ing the original author and only person to ever tou=
ch that
> file would have been appreciated.
Okay, it's my fault, I will update it, thanks.
>=20
> Rasmus