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Date:   Tue, 27 Oct 2020 16:31:32 -0700
From:   Nicolin Chen <nicoleotsuka@gmail.com>
To:     Thierry Reding <thierry.reding@gmail.com>
Cc:     Krzysztof Kozlowski <krzk@kernel.org>, robh+dt@kernel.org,
        jonathanh@nvidia.com, linux-tegra@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 4/5] dt-bindings: memory: tegra: Add missing swgroups
Message-ID: <20201027233132.GA11164@Asurada-Nvidia>
References: <20201008003746.25659-1-nicoleotsuka@gmail.com>
 <20201008003746.25659-5-nicoleotsuka@gmail.com>
 <20201009122110.GD458338@ulmo>
 <20201009155218.GA4469@Asurada-Nvidia>
 <20201026201758.GD248919@kozik-lap>
 <20201027125506.GA1822510@ulmo>
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On Tue, Oct 27, 2020 at 01:55:06PM +0100, Thierry Reding wrote:

> This does indeed look correct, based on what registers exist for these.
> It'd be good to know how Nicolin expects these to be used, since these
> are currently not listed in device tree. There's certainly some like

Judging from our downstream code, I don't actually expect all of
them will be used, except some being used yet not got upstream.

> TSEC or NVDEC that we don't support (yet) upstream, but things like DC1
> and HC1 already have equivalents that we use, so I'm not sure how we'll
> integrate these new ones.

Downstream code groups those equivalents swgroups, so I think we
can do similarly using tegra_smmu_group_soc like the existing one
for display, if any of them gets upstream someday.