Received: by 2002:a05:6a10:9e8c:0:0:0:0 with SMTP id y12csp43562pxx; Wed, 28 Oct 2020 17:37:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy5m/n035Y/TX1LBCvURYd23tYcAurPf5MNPd2ZOH91Qrba0huWM+aucbMkp8dhQpqqnu9X X-Received: by 2002:a17:906:cc8b:: with SMTP id oq11mr1786171ejb.116.1603931831738; Wed, 28 Oct 2020 17:37:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1603931831; cv=none; d=google.com; s=arc-20160816; b=qMFP7O3Okt9YxcNJyZ97G2Mt6X4jBQjQuxYr+dKVPGcZ/pD35hTQO0SCu8c4S0Iw6w f7FC9p5ieByngr4lv1uwVzpeosPEuOGj1VtUZJcU1o3fEcJmvNeGnS8TsgSpIYdw/40f ZVC7yDlknyG5gxZ9g7OjQvVlch0Q+C5vHW7iMfHNzTOB/e7CEhzg1LR3bZBhHtuidDGu +JytvLUSzUAD5TxzuEW13jJkUACL/qyaRO55T6UY3sTjr9RM8FWJ+aJtPzWd/BaU/Bep aoReubbFOceC953dbG7w1bcnFYoIRvgpsBwY4H5w1UWG+U2cPX857G6Mmc8ZKTYG2Jd9 uP1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=1KMEoItmYOZOGAtS6DFo4XfP45bsfqzYjnq1OSZUv00=; b=hp1l8C2R0nnz5uh63nJJVx6lg4hTdnqva7g1P4vQ/3+MbSkc+vV2AHwjxdb6q3Cbxd rUgVVDjeYqRwFlJJsVbsz0Fn+l6rI/68RajjaKHCVVgqSaNiEvj+R6fD6PtV1PWDw5oC Bl3gOidJinVaegmlnjSC1Tt8Zo6lfP8WiieIBlUUqbznl/rUmSgH5wXFHZ2RDXlTW48D /wBZU8q/uqn4KQOsdwHsJ8+I2zHF5KSFdvwSF2X18BKX9YKGhhndgBRzSj0aChs6wlZz glHUuBE86vsT/T74CcUbxlN7n7HU/QDDpAyVJFqgBR70XJ9vIWJKiBHxEU1wQnUp+xXp 8AIA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id bq7si670770ejb.212.2020.10.28.17.36.50; Wed, 28 Oct 2020 17:37:11 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730541AbgJ1WKc (ORCPT + 99 others); Wed, 28 Oct 2020 18:10:32 -0400 Received: from foss.arm.com ([217.140.110.172]:39114 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730462AbgJ1WKT (ORCPT ); Wed, 28 Oct 2020 18:10:19 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CF9E41763; Wed, 28 Oct 2020 15:10:18 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.1.197.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E0EFD3F68F; Wed, 28 Oct 2020 15:10:17 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Cc: mathieu.poirier@linaro.org, mike.leach@linaro.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org, Suzuki K Poulose Subject: [PATCH v3 16/26] coresight: etm4x: Check for Software Lock Date: Wed, 28 Oct 2020 22:09:35 +0000 Message-Id: <20201028220945.3826358-18-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20201028220945.3826358-1-suzuki.poulose@arm.com> References: <20201028220945.3826358-1-suzuki.poulose@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Software lock is not implemented for system instructions based accesses. So, skip the lock register access in such cases. Signed-off-by: Suzuki K Poulose --- .../coresight/coresight-etm4x-core.c | 40 ++++++++++++------- 1 file changed, 25 insertions(+), 15 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index a5c914b16e59..a12d58a04c5d 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -121,6 +121,21 @@ static void etm4_os_lock(struct etmv4_drvdata *drvdata) isb(); } +static void etm4_cs_lock(struct etmv4_drvdata *drvdata, + struct csdev_access *csa) +{ + /* Software Lock is only accessible via memory mapped interface */ + if (csa->io_mem) + CS_LOCK(csa->base); +} + +static void etm4_cs_unlock(struct etmv4_drvdata *drvdata, + struct csdev_access *csa) +{ + if (csa->io_mem) + CS_UNLOCK(csa->base); +} + static bool etm4_arch_supported(u8 arch) { /* Mask out the minor version number */ @@ -160,8 +175,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) struct device *etm_dev = &csdev->dev; struct csdev_access *csa = &csdev->access; - CS_UNLOCK(drvdata->base); - + etm4_cs_unlock(drvdata, csa); etm4_os_unlock(drvdata); rc = coresight_claim_device_unlocked(csdev); @@ -262,7 +276,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) isb(); done: - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n", drvdata->cpu, rc); @@ -519,7 +533,7 @@ static void etm4_disable_hw(void *info) struct csdev_access *csa = &csdev->access; int i; - CS_UNLOCK(drvdata->base); + etm4_cs_unlock(drvdata, csa); if (!drvdata->skip_power_up) { /* power can be removed from the trace unit now */ @@ -560,8 +574,7 @@ static void etm4_disable_hw(void *info) } coresight_disclaim_device_unlocked(csdev); - - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); dev_dbg(&drvdata->csdev->dev, "cpu: %d disable smp call done\n", drvdata->cpu); @@ -671,8 +684,7 @@ static void etm4_init_arch_data(void *info) /* Make sure all registers are accessible */ etm4_os_unlock_csa(drvdata, csa); - - CS_UNLOCK(drvdata->base); + etm4_cs_unlock(drvdata, csa); /* find all capabilities of the tracing unit */ etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0); @@ -837,7 +849,7 @@ static void etm4_init_arch_data(void *info) drvdata->nrseqstate = BMVAL(etmidr5, 25, 27); /* NUMCNTR, bits[30:28] number of counters available for tracing */ drvdata->nr_cntr = BMVAL(etmidr5, 28, 30); - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); } /* Set ELx trace filter access in the TRCVICTLR register */ @@ -1218,8 +1230,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) dsb(sy); isb(); - CS_UNLOCK(drvdata->base); - + etm4_cs_unlock(drvdata, csa); /* Lock the OS lock to disable trace and external debugger access */ etm4_os_lock(drvdata); @@ -1330,7 +1341,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU), TRCPDCR); out: - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); return ret; } @@ -1341,8 +1352,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base); struct csdev_access *csa = &tmp_csa; - CS_UNLOCK(drvdata->base); - + etm4_cs_unlock(drvdata, csa); etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET); etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR); @@ -1426,7 +1436,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) /* Unlock the OS lock to re-enable trace and external debug access */ etm4_os_unlock(drvdata); - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); } static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, -- 2.24.1