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From:   =?iso-8859-1?Q?Jan_Kundr=E1t?= <jan.kundrat@cesnet.cz>
To:     Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc:     Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Jiri Slaby <jirislaby@kernel.org>,
        <linux-serial@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        Mark Brown <broonie@kernel.org>,
        Andy Shevchenko <andy.shevchenko@gmail.com>,
        <linux-spi@vger.kernel.org>
Subject: Re: [PATCH v2] serial: max310x: rework RX interrupt handling
Date:   Wed, 28 Oct 2020 17:20:24 +0100
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On =C4=8Dtvrtek 1. =C5=99=C3=ADjna 2020 9:44:15 CEST, Thomas Petazzoni wrote:=

> Currently, the RX interrupt logic uses the RXEMPTY interrupt, with the
> RXEMPTYINV bit set, which means we get an RX interrupt as soon as the
> RX FIFO is non-empty.
>
> However, with the MAX310X having a FIFO of 128 bytes, this makes very
> poor use of the FIFO: we trigger an interrupt as soon as the RX FIFO
> has one byte, which means a lot of interrupts, each only collecting a
> few bytes from the FIFO, causing a significant CPU load.

Thanks for taking the time to write this patch. We're using MAX14830 on a=20
Clearfog Base board via a 26 MHz SPI bus. Our code polls a custom=20
peripheral over UART at 115200 baud ten times a second; the messages are=20
typically shorter than 50 chars. Before this patch, `perf top --sort=20
comm,dso` showed about 28% CPU load for the corresponding SPI kthread,=20
after applying this patch it's between 3 and 5%. That's cool :).

Tested-by: Jan Kundr=C3=A1t <jan.kundrat@cesnet.cz>
Reviewed-by: Jan Kundr=C3=A1t <jan.kundrat@cesnet.cz>

(but see below, please)

> +=09/* Enable LSR, RX FIFO trigger, CTS change interrupts */
> +=09val =3D MAX310X_IRQ_LSR_BIT  | MAX310X_IRQ_RXFIFO_BIT |=20
> MAX310X_IRQ_TXEMPTY_BIT;
>  =09max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT);=


This comment doesn't fully match that code, and also the effective value=20
that is written to the register is split into two statements. What about=20
just:

+=09/* Enable LSR, RX FIFO trigger, TX FIFO empty, CTS change interrupts */
+ =09max310x_port_write(port, MAX310X_IRQEN_REG, MAX310X_IRQ_LSR_BIT |=20
MAX310X_IRQ_RXFIFO_BIT | MAX310X_IRQ_TXEMPTY_BIT | MAX310X_IRQ_CTS_BIT);

With kind regards,
Jan