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[23.128.96.18]) by mx.google.com with ESMTP id s18si1406332ejr.128.2020.10.29.02.08.53; Thu, 29 Oct 2020 02:09:16 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=lbji3myH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729522AbgJ2Ijk (ORCPT + 99 others); Thu, 29 Oct 2020 04:39:40 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:11563 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727555AbgJ2IjJ (ORCPT ); Thu, 29 Oct 2020 04:39:09 -0400 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Wed, 28 Oct 2020 22:18:40 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 29 Oct 2020 05:18:57 +0000 Received: from vidyas-desktop.nvidia.com (172.20.13.39) by mail.nvidia.com (172.20.187.15) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Thu, 29 Oct 2020 05:18:53 +0000 From: Vidya Sagar To: , , , , , , , CC: , , , , , , Subject: [PATCH V2 2/4] PCI: tegra: Map configuration space as nGnRnE Date: Thu, 29 Oct 2020 10:48:37 +0530 Message-ID: <20201029051839.11245-3-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201029051839.11245-1-vidyas@nvidia.com> References: <20201029051839.11245-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1603948720; bh=Z8voXAw6EbjwLVqEHgC9ep3B8F2TRloMTeKeWZiHZOY=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=lbji3myHofempJg4PpP6JxTk2IJUX+VfbBEe5+h5cLW2LV58+2o9k/zHDAcdkxPU8 zP52gWcf7AEntxB+a7PE+Nemqr/axvraN27vYehuowG6apDMze216kS9rgsXpzIQja V2Bu1pOrW3WB9SjP9MheozI8k0/nMItG7Q13WRt/intnLrFwPkDmijBQaR39ULFjHY R8Vl4dfQo4S/SwJHrpPDxnMkF3QPW8GdrwaHkdTJ7nSMhDSq0gg5sWz4sYA0aitMRW HpQzl0fUj4PJhfTmsCV2UAbI74dv+a62aKaCO8bFFEiGRxQCvs0gNcAzCsD9jgMDti bkdnqiQkEL9ew== Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As specified in the comment for pci_remap_cfgspace() define in arch/arm64/include/asm/io.h file, PCIe configuration space should be mapped as nGnRnE. Hence changing to dev_pci_remap_cfgspace() from devm_ioremap_resource() for mapping DBI space as that is nothing but the root port's own configuration space. Signed-off-by: Vidya Sagar --- V2: * Changed 'Strongly Ordered' to 'nGnRnE' drivers/pci/controller/dwc/pcie-tegra194.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index b172b1d49713..7a0c64436861 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2108,7 +2108,9 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev) } pcie->dbi_res = dbi_res; - pci->dbi_base = devm_ioremap_resource(dev, dbi_res); + pci->dbi_base = devm_pci_remap_cfgspace(dev, + dbi_res->start, + resource_size(dbi_res)); if (IS_ERR(pci->dbi_base)) return PTR_ERR(pci->dbi_base); -- 2.17.1