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[23.128.96.18]) by mx.google.com with ESMTP id w1si3359512edf.589.2020.10.29.18.54.20; Thu, 29 Oct 2020 18:54:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@mg.codeaurora.org header.s=smtp header.b=JJAaeHIg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726355AbgJ3BwS (ORCPT + 99 others); Thu, 29 Oct 2020 21:52:18 -0400 Received: from z5.mailgun.us ([104.130.96.5]:43112 "EHLO z5.mailgun.us" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726320AbgJ3BwQ (ORCPT ); Thu, 29 Oct 2020 21:52:16 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1604022736; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=uDkB0j/nHi+yko6XBTUhnB4d9dN2gZbTP2OcDO6gRrY=; b=JJAaeHIgk/4yew1pdA4kd8mjN+pSg5eOZrq1IjLwnw2mzSvQ4/ocWDUrrBEHv/HxmbuyDwh/ E+zmBwvFYfO5nkbzP3XXV8QtUKffTuhVvoCBdoFoCUb4IKsX398L6w00/DxXx5z40zPxYTHp 3nU4OZGddictDgsssDJPYKdj6+w= X-Mailgun-Sending-Ip: 104.130.96.5 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n04.prod.us-west-2.postgun.com with SMTP id 5f9b71cfc3d7c9858ad1431f (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Fri, 30 Oct 2020 01:52:15 GMT Sender: bbhatt=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id DAD73C433CB; Fri, 30 Oct 2020 01:52:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=ALL_TRUSTED,BAYES_00,SPF_FAIL, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from malabar-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: bbhatt) by smtp.codeaurora.org (Postfix) with ESMTPSA id E811AC433C8; Fri, 30 Oct 2020 01:52:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E811AC433C8 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=bbhatt@codeaurora.org From: Bhaumik Bhatt To: manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, hemantk@codeaurora.org, jhugo@codeaurora.org, linux-kernel@vger.kernel.org, Bhaumik Bhatt Subject: [PATCH v2 09/12] bus: mhi: core: Check for IRQ availability during registration Date: Thu, 29 Oct 2020 18:52:00 -0700 Message-Id: <1604022723-34578-10-git-send-email-bbhatt@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604022723-34578-1-git-send-email-bbhatt@codeaurora.org> References: <1604022723-34578-1-git-send-email-bbhatt@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Current design allows a controller to register with MHI successfully without the need to have any IRQs available for use. If no IRQs are available, power up requests to MHI can fail after a successful registration with MHI. Improve the design by checking for the number of IRQs available sooner within the mhi_regsiter_controller() API as it is required to be specified by the controller. Signed-off-by: Bhaumik Bhatt --- drivers/bus/mhi/core/init.c | 2 +- drivers/bus/mhi/core/pm.c | 3 --- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c index 23b6dd6..5dd9e39 100644 --- a/drivers/bus/mhi/core/init.c +++ b/drivers/bus/mhi/core/init.c @@ -858,7 +858,7 @@ int mhi_register_controller(struct mhi_controller *mhi_cntrl, if (!mhi_cntrl->runtime_get || !mhi_cntrl->runtime_put || !mhi_cntrl->status_cb || !mhi_cntrl->read_reg || - !mhi_cntrl->write_reg) + !mhi_cntrl->write_reg || !mhi_cntrl->nr_irqs) return -EINVAL; ret = parse_config(mhi_cntrl, config); diff --git a/drivers/bus/mhi/core/pm.c b/drivers/bus/mhi/core/pm.c index 06adea2..1d04e401 100644 --- a/drivers/bus/mhi/core/pm.c +++ b/drivers/bus/mhi/core/pm.c @@ -926,9 +926,6 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl) dev_info(dev, "Requested to power ON\n"); - if (mhi_cntrl->nr_irqs < 1) - return -EINVAL; - /* Supply default wake routines if not provided by controller driver */ if (!mhi_cntrl->wake_get || !mhi_cntrl->wake_put || !mhi_cntrl->wake_toggle) { -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project