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Fri, 30 Oct 2020 09:32:29 +0000 From: Ioana Ciornei To: Shawn Guo CC: "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH 2/9] arm64: dts: ls1088ardb: add QSGMII PHY nodes Thread-Topic: [PATCH 2/9] arm64: dts: ls1088ardb: add QSGMII PHY nodes Thread-Index: AQHWkz9K9Yuz4h4Kq0Kl0DjjHE9FKamves0AgACd3gA= Date: Fri, 30 Oct 2020 09:32:29 +0000 Message-ID: <20201030093228.4b7tvsa2vnam5nj2@skbuf> References: <20200925132503.30206-1-ioana.ciornei@nxp.com> <20200925132503.30206-3-ioana.ciornei@nxp.com> <20201030000725.GT28755@dragon> In-Reply-To: <20201030000725.GT28755@dragon> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: kernel.org; dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=nxp.com; x-originating-ip: [188.25.2.177] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: 9a928ba8-7529-4bf1-8680-08d87cb6b898 x-ms-traffictypediagnostic: VI1PR04MB7199: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:4941; 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charset="us-ascii" Content-ID: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: VI1PR0402MB3871.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9a928ba8-7529-4bf1-8680-08d87cb6b898 X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Oct 2020 09:32:29.5321 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: eCdctMv6BKyZYIa04HrlaH5PyiSo481W1RpSFgPgVKU7xzWTGb20T6Y/JbgR7nkbiKu1ZklFKgixSO/anQQDhQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB7199 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Oct 30, 2020 at 08:07:26AM +0800, Shawn Guo wrote: > On Fri, Sep 25, 2020 at 04:24:56PM +0300, Ioana Ciornei wrote: > > Annotate the external MDIO1 node and describe the 8 QSGMII PHYs found o= n > > the LS1088ARDB board and add phy-handles for DPMACs 3-10 to its > > associated PHY. Also, add the internal PCS MDIO nodes for the internal > > MDIO buses found on the LS1088A SoC along with their internal PCS PHY > > and link the corresponding DPMAC to the PCS through the pcs-handle. > >=20 > > Signed-off-by: Ioana Ciornei > > --- > > .../boot/dts/freescale/fsl-ls1088a-rdb.dts | 100 ++++++++++++++++++ > > .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 50 +++++++++ > > 2 files changed, 150 insertions(+) > >=20 > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/a= rm64/boot/dts/freescale/fsl-ls1088a-rdb.dts > > index 5633e59febc3..d7886b084f7f 100644 > > --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts > > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts > > @@ -17,6 +17,98 @@ / { > > compatible =3D "fsl,ls1088a-rdb", "fsl,ls1088a"; > > }; (...) > > +&emdio1 { > > + status =3D "okay"; > > + > > + mdio1_phy1: emdio1_phy@1 { >=20 > If this is an Ethernet PHY device, please use generic node name like > 'ethernet-phy'. Also the unit-address in node name should match 'reg' > property. Yes, it is. I'll rename them and use the reg as the unit-address. (...) > > + pcs_mdio3: mdio@8c0f000 { > > + compatible =3D "fsl,fman-memac-mdio"; > > + reg =3D <0x0 0x8c0f000 0x0 0x1000>; > > + little-endian; > > + #address-cells =3D <1>; > > + #size-cells =3D <0>; > > + status =3D "disabled"; > > + > > + pcs3_0: pcs-phy@0 { >=20 > ethernet-phy@0? >=20 Will change. Ioana=