Received: by 2002:a05:6a10:9e8c:0:0:0:0 with SMTP id y12csp1493352pxx; Fri, 30 Oct 2020 11:14:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy5Mdlj7k7H0exjDPtlC5rxjs1TUmtKYtTcJLbcAoP2T7eRTNHwutPm5JmeMGy1GTy2IAVa X-Received: by 2002:a05:6402:1482:: with SMTP id e2mr3981714edv.36.1604081659043; Fri, 30 Oct 2020 11:14:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1604081659; cv=none; d=google.com; s=arc-20160816; b=hVmfRhQ4yJBw97fDFl0CilKnxScaVIS0wj2bf6g7vNZwSXyok2enxBrtH3RBKsAbTk MUpF1OLU5gx+QPx7NiNDQ47Shp0O5GnpXUge3RnC638F+2jfOsiBKFUO7LEjPhqdJKYR iSR04wY33z4ICjypKn8kPnDdBwtpY6bxDXKDIxjIv6P6B9KjF5e50C80+nKOW+wuA53U 3Y+swWZLF6XWODwiP/B9BHLwkkr9f/aWa3rIqLeDeU6km4u1UOcUmh4dXIBMgJ/pgskW Y3kCqm9AARJsFkSHTNpc7QZ9e9DdFWUfcJje/uemA6j/Vl9EVZDm+lH9Uh0jK80GSbE8 Ou3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:user-agent:in-reply-to:content-disposition :mime-version:references:message-id:subject:cc:to:from:date; bh=0MpeVc2hEyinZk5K1QwFpNKgr5jeIiK7gMRADiny3q0=; b=uaupxhrkgrazUnQpVZzW9oJ9iJHQ1Y3KrNkWMfAr8DmKgY0t69Ge6LQD2etGB2ES4k fpPZ5LeOT6yBJtCIM7t/pGiUdnB7DJojdes9h/uZPxged/P0cf5BQBCw0DCElfqgvPqe x9JAmdwSEmFVt0128O5eSzBr1ciiX1pEeVb0wImK1AZoUp9rn6d5ZeP0r98QAEJ7FPap b/jenxGSR1l++kNkowbERBezmPH693hJaXJb412CUiw/gTipMN6QQkJ2Gv9xiYqGLXo+ TxlB8kWi9CHmpwrZxKmHdtGFnfoJsZVGfSxNEN613UbtEM0EiEJagw8Wr0t+LTxCVoGJ Idng== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id h34si4713317edd.72.2020.10.30.11.13.55; Fri, 30 Oct 2020 11:14:19 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726858AbgJ3SMd (ORCPT + 99 others); Fri, 30 Oct 2020 14:12:33 -0400 Received: from mail.kernel.org ([198.145.29.99]:54602 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725844AbgJ3SMa (ORCPT ); Fri, 30 Oct 2020 14:12:30 -0400 Received: from gaia (unknown [95.145.162.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id D3A17206E5; Fri, 30 Oct 2020 18:11:37 +0000 (UTC) Date: Fri, 30 Oct 2020 18:11:35 +0000 From: Catalin Marinas To: Nicolas Saenz Julienne Cc: robh+dt@kernel.org, hch@lst.de, ardb@kernel.org, linux-kernel@vger.kernel.org, robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, jeremy.linton@arm.com, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, will@kernel.org, lorenzo.pieralisi@arm.com, guohanjun@huawei.com, linux-acpi@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v5 0/7] arm64: Default to 32-bit wide ZONE_DMA Message-ID: <20201030181134.GE23196@gaia> References: <20201029172550.3523-1-nsaenzjulienne@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201029172550.3523-1-nsaenzjulienne@suse.de> User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Oct 29, 2020 at 06:25:43PM +0100, Nicolas Saenz Julienne wrote: > Ard Biesheuvel (1): > arm64: mm: Set ZONE_DMA size based on early IORT scan > > Nicolas Saenz Julienne (6): > arm64: mm: Move reserve_crashkernel() into mem_init() > arm64: mm: Move zone_dma_bits initialization into zone_sizes_init() > of/address: Introduce of_dma_get_max_cpu_address() > of: unittest: Add test for of_dma_get_max_cpu_address() > arm64: mm: Set ZONE_DMA size based on devicetree's dma-ranges > mm: Remove examples from enum zone_type comment Thanks for putting this together. I had a minor comment but the patches look fine to me. We still need an ack from Rob on the DT patch and I can queue the series for 5.11. Could you please also test the patch below on top of this series? It's the removal of the implied DMA offset in the max_zone_phys() calculation. --------------------------8<----------------------------- From 3ae252d888be4984a612236124f5b099e804c745 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Fri, 30 Oct 2020 18:07:34 +0000 Subject: [PATCH] arm64: Ignore any DMA offsets in the max_zone_phys() calculation Currently, the kernel assumes that if RAM starts above 32-bit (or zone_bits), there is still a ZONE_DMA/DMA32 at the bottom of the RAM and such constrained devices have a hardwired DMA offset. In practice, we haven't noticed any such hardware so let's assume that we can expand ZONE_DMA32 to the available memory if no RAM below 4GB. Similarly, ZONE_DMA is expanded to the 4GB limit if no RAM addressable by zone_bits. Signed-off-by: Catalin Marinas --- arch/arm64/mm/init.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c index 095540667f0f..362160e16fb2 100644 --- a/arch/arm64/mm/init.c +++ b/arch/arm64/mm/init.c @@ -175,14 +175,21 @@ static void __init reserve_elfcorehdr(void) #endif /* CONFIG_CRASH_DUMP */ /* - * Return the maximum physical address for a zone with a given address size - * limit. It currently assumes that for memory starting above 4G, 32-bit - * devices will use a DMA offset. + * Return the maximum physical address for a zone accessible by the given bits + * limit. If the DRAM starts above 32-bit, expand the zone to the maximum + * available memory, otherwise cap it at 32-bit. */ static phys_addr_t __init max_zone_phys(unsigned int zone_bits) { - phys_addr_t offset = memblock_start_of_DRAM() & GENMASK_ULL(63, zone_bits); - return min(offset + (1ULL << zone_bits), memblock_end_of_DRAM()); + phys_addr_t zone_mask = (1ULL << zone_bits) - 1; + phys_addr_t phys_start = memblock_start_of_DRAM(); + + if (!(phys_start & U32_MAX)) + zone_mask = PHYS_ADDR_MAX; + else if (!(phys_start & zone_mask)) + zone_mask = U32_MAX; + + return min(zone_mask + 1, memblock_end_of_DRAM()); } static void __init zone_sizes_init(unsigned long min, unsigned long max)