Received: by 2002:a05:6a10:9e8c:0:0:0:0 with SMTP id y12csp1679895pxx; Fri, 30 Oct 2020 16:38:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz9mA56M4CtSc8qd8A1xFeOAbDcO3C+hDm9MhTlNFinbMvPxXqXWZPIlc9YeHIYMc3O96HD X-Received: by 2002:a17:906:b043:: with SMTP id bj3mr4783785ejb.543.1604101098434; Fri, 30 Oct 2020 16:38:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1604101098; cv=none; d=google.com; s=arc-20160816; b=r1TbOD4/kOsrkVH8wzgaku5xflPv9AhM7R3H0fXzyIHW6xZSI7hqn24bv5t/o1/Xms DUVJvi679ce8X5x6jlqS33HgKTY/js0X8RkngjP5jmEEamAu0xfUuybalmGe8AL+ZhP6 rpH2iS28+QYwEB1dotLILXtvRho1lBIGPZOPSj68hwVKmYboBcpjrC0c1hEYb5rTfkmX 64oCUJxL5PgRZ65uX7XjUCl5GnWlln8WXigaG8qZsQKrck+A7nu42YHwdqtNXeI208b1 agUUhy2mDHSuB6ycKPNWr63mufGLEmOBTkthRVp7dRhfs0/4AJK/gTWweUcGQYXlDOkZ uuFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:cc:to:from:date; bh=DsoUBKatvWuib0K1oj3FVul6PCy0M4UzV8R1NAuWa44=; b=Tbu6JTSzZ45Pilq57P29LMmGMZNPNIH1qs06DvXFqU3VM/bamfOZnIz6zfUtGw2Acl tIbUx688PckbquzWc1cM7IivTAhI1ixEuSDxOEjGDH/IfwdJVZFfiTv+qiODCYogDn6+ TiNc23me4DVNHzlpKjOMsZP84tDgSoakxaS8xmQqWp+LPJ1K3C8tqb8ryRP9hVQBULdN qvRX2FoPOx2Cos+eT3Q1YGn7BIU06WGo2Gph8lmFVYPFFN3Q629j0bZOn82Ahb0jPZly /NUdwIZmcXfVyfETaqY4Vau/c7Iftx9THHNAGYsyzp4T6cyQyZUH3Zgm65tWUhv9S4zE hq7g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id v19si5384484ejb.643.2020.10.30.16.37.55; Fri, 30 Oct 2020 16:38:18 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725789AbgJ3Xgl (ORCPT + 99 others); Fri, 30 Oct 2020 19:36:41 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:55664 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725446AbgJ3Xgl (ORCPT ); Fri, 30 Oct 2020 19:36:41 -0400 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1kYdwZ-004RBd-P3; Sat, 31 Oct 2020 00:36:27 +0100 Date: Sat, 31 Oct 2020 00:36:27 +0100 From: Andrew Lunn To: Heiner Kallweit Cc: Ioana Ciornei , Russell King , Jakub Kicinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Ioana Ciornei , Alexandru Ardelean , Andre Edich , Antoine Tenart , Baruch Siach , Christophe Leroy , Dan Murphy , Divya Koppera , Florian Fainelli , Hauke Mehrtens , Jerome Brunet , Kavya Sree Kotagiri , Linus Walleij , Marco Felsch , Marek Vasut , Martin Blumenstingl , Mathias Kresin , Maxim Kochetkov , Michael Walle , Neil Armstrong , Nisar Sayed , Oleksij Rempel , Philippe Schenker , Willy Liu , Yuiko Oshino Subject: Re: [PATCH net-next 00/19] net: phy: add support for shared interrupts (part 1) Message-ID: <20201030233627.GA1054829@lunn.ch> References: <20201029100741.462818-1-ciorneiioana@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > > - Every PHY driver gains a .handle_interrupt() implementation that, for > > the most part, would look like below: > > > > irq_status = phy_read(phydev, INTR_STATUS); > > if (irq_status < 0) { > > phy_error(phydev); > > return IRQ_NONE; > > } > > > > if (irq_status == 0) > > Here I have a concern, bits may be set even if the respective interrupt > source isn't enabled. Therefore we may falsely blame a device to have > triggered the interrupt. irq_status should be masked with the actually > enabled irq source bits. Hi Heiner I would say that is a driver implementation detail, for each driver to handle how it needs to handle it. I've seen some hardware where the interrupt status is already masked with the interrupt enabled bits. I've soon other hardware where it is not. For example code, what is listed above is O.K. The real implementation in a driver need knowledge of the hardware. Andrew