Message-ID: <44E3A572.20600@hp.com>
Date: Wed, 16 Aug 2006 16:08:34 -0700
From: Rick Jones <rick.jones2@hp.com>
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To: Linas Vepstas <linas@austin.ibm.com>
Cc: Arnd Bergmann <arnd@arndb.de>, David Miller <davem@davemloft.net>,
       jeff@garzik.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
       linuxppc-dev@ozlabs.org, jklewis@us.ibm.com, Jens.Osterkamp@de.ibm.com,
       akpm@osdl.org
Subject: Re: [PATCH 1/2]: powerpc/cell spidernet bottom half
References: <44E34825.2020105@garzik.org> <44E38157.4070805@garzik.org>	<20060816.134640.115912460.davem@davemloft.net>	<200608162324.47235.arnd@arndb.de> <20060816225558.GM20551@austin.ibm.com>
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Linas Vepstas wrote:
> On Wed, Aug 16, 2006 at 11:24:46PM +0200, Arnd Bergmann wrote:
> 
>>it only
>>seems to be hard to make it go fast using any of them. 
> 
> 
> Last round of measurements seemed linear for packet sizes between
> 60 and 600 bytes, suggesting that the hardware can handle a 
> maximum of 120K descriptors/second, independent of packet size.
> I don't know why this is.

DMA overhead perhaps?  If it takes so many micro/nanoseconds to get a 
DMA going....  That used to be a reason the Tigon2 had such low PPS 
rates and issues with multiple buffer packets and a 1500 byte MTU - it 
had rather high DMA setup latency, and then if you put it into a system 
with highish DMA read/write latency... well that didn't make it any 
better :)

rick jones
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