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[2003:ea:8f23:2800:354c:e90a:781b:bae1]) by smtp.googlemail.com with ESMTPSA id j127sm8180311wma.31.2020.10.31.03.18.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 31 Oct 2020 03:18:23 -0700 (PDT) Subject: Re: [PATCH net-next 00/19] net: phy: add support for shared interrupts (part 1) To: Andrew Lunn Cc: Ioana Ciornei , Russell King , Jakub Kicinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Ioana Ciornei , Alexandru Ardelean , Andre Edich , Antoine Tenart , Baruch Siach , Christophe Leroy , Dan Murphy , Divya Koppera , Florian Fainelli , Hauke Mehrtens , Jerome Brunet , Kavya Sree Kotagiri , Linus Walleij , Marco Felsch , Marek Vasut , Martin Blumenstingl , Mathias Kresin , Maxim Kochetkov , Michael Walle , Neil Armstrong , Nisar Sayed , Oleksij Rempel , Philippe Schenker , Willy Liu , Yuiko Oshino References: <20201029100741.462818-1-ciorneiioana@gmail.com> <20201030233627.GA1054829@lunn.ch> From: Heiner Kallweit Message-ID: Date: Sat, 31 Oct 2020 11:18:18 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.4.0 MIME-Version: 1.0 In-Reply-To: <20201030233627.GA1054829@lunn.ch> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 31.10.2020 00:36, Andrew Lunn wrote: >>> - Every PHY driver gains a .handle_interrupt() implementation that, for >>> the most part, would look like below: >>> >>> irq_status = phy_read(phydev, INTR_STATUS); >>> if (irq_status < 0) { >>> phy_error(phydev); >>> return IRQ_NONE; >>> } >>> >>> if (irq_status == 0) >> >> Here I have a concern, bits may be set even if the respective interrupt >> source isn't enabled. Therefore we may falsely blame a device to have >> triggered the interrupt. irq_status should be masked with the actually >> enabled irq source bits. > > Hi Heiner > Hi Andrew, > I would say that is a driver implementation detail, for each driver to > handle how it needs to handle it. I've seen some hardware where the > interrupt status is already masked with the interrupt enabled > bits. I've soon other hardware where it is not. > Sure, I just wanted to add the comment before others simply copy and paste this (pseudo) code. And in patch 9 (aquantia) and 18 (realtek) it is used as is. And IIRC at least the Aquantia PHY doesn't mask the interrupt status. > For example code, what is listed above is O.K. The real implementation > in a driver need knowledge of the hardware. > > Andrew > . > Heiner