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[23.128.96.18]) by mx.google.com with ESMTP id bu10si7009590edb.54.2020.10.31.07.52.46; Sat, 31 Oct 2020 07:53:08 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=HTqYXnVA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727877AbgJaOvG (ORCPT + 99 others); Sat, 31 Oct 2020 10:51:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726115AbgJaOvG (ORCPT ); Sat, 31 Oct 2020 10:51:06 -0400 Received: from mail-ej1-x644.google.com (mail-ej1-x644.google.com [IPv6:2a00:1450:4864:20::644]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD0DDC0617A6; Sat, 31 Oct 2020 07:51:05 -0700 (PDT) Received: by mail-ej1-x644.google.com with SMTP id s15so12545718ejf.8; Sat, 31 Oct 2020 07:51:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:date:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=xeoqSsCGy6lTHKb5i/FB3Sn7FnwCv5pc3NVImeJNRB8=; b=HTqYXnVAZEYca4dwQIlJytP+mRVD8IFnsBMPMlPmYjk2ikBIo2b31cfj/1J6nkOjGA eSV8BM6Q0jdjN2tTB8E8I4Pcvf4MVdLL6uZ8doy3F2jK4IxmCXL23TJpFVUYsIjTqPQn g0hb/2D/hc6VwQpuXBRED1+Ufty8s/jf+QuTk3uVyYBJfFq9M+Ekn9qAzufolqLAjqxS KGq8toRd8BqqSoz4ICGbS0cLnLidFCUtOYTIyjFEmaZWiTieOfQRdvoDxoS91RV7l63n 6lzGPuhzsTj6Gil1b2SUZPo7vFbICOMUsNoxiLOrZoXfeZpU2rkqUYveIbX4rfgaFM+x iv7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:date:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=xeoqSsCGy6lTHKb5i/FB3Sn7FnwCv5pc3NVImeJNRB8=; b=KWg8aKfYrXJwUzsTlelc0Am27/FIgTQtjU+uno0//W0vhJfB6S9UP8sr0lLuZ9hI88 KWuZUKKOV0gGSgLlEtVVU3+uxMXAbreo/+Sht6VVxDVfTTHuD9NlFB2g9WjjRdIBp1QZ t7tMVCNjlYo1rFF7TtyMqSt9C/sqKxwc3kJvl3oUaVscHYGK8+JLzb6uDokEBruXjrQr AZeflYQGwtROm9j2hCo0FiBwBuieR/9hPZM/OHyd1phwCHxif+fo5WdTZhqHttGxvDhz Dy8fpXUl8X19Q1BqqhRuweWkScWeLb5yp9yIuwDLlf+hl3GeiCRWKDxU9r39XU13Y9e+ f6Jw== X-Gm-Message-State: AOAM531HlDWVQjJZ9QG3EUzwS/Y4xidb0thikUVH8ZMCumW4c8Hzwlhz FKSwU0MpCgHiJnde86nQ6yU= X-Received: by 2002:a17:906:3acd:: with SMTP id z13mr7716765ejd.118.1604155864422; Sat, 31 Oct 2020 07:51:04 -0700 (PDT) Received: from skbuf ([188.25.2.177]) by smtp.gmail.com with ESMTPSA id ok21sm4990707ejb.96.2020.10.31.07.51.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Oct 2020 07:51:03 -0700 (PDT) From: Ioana Ciornei X-Google-Original-From: Ioana Ciornei Date: Sat, 31 Oct 2020 16:51:01 +0200 To: Andrew Lunn Cc: Heiner Kallweit , Ioana Ciornei , Russell King , Jakub Kicinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Ioana Ciornei , Alexandru Ardelean , Andre Edich , Antoine Tenart , Baruch Siach , Christophe Leroy , Dan Murphy , Divya Koppera , Florian Fainelli , Hauke Mehrtens , Jerome Brunet , Kavya Sree Kotagiri , Linus Walleij , Marco Felsch , Marek Vasut , Martin Blumenstingl , Mathias Kresin , Maxim Kochetkov , Michael Walle , Neil Armstrong , Nisar Sayed , Oleksij Rempel , Philippe Schenker , Willy Liu , Yuiko Oshino Subject: Re: [PATCH net-next 00/19] net: phy: add support for shared interrupts (part 1) Message-ID: <20201031145101.ehxb2boekevppu3d@skbuf> References: <20201029100741.462818-1-ciorneiioana@gmail.com> <20201030233627.GA1054829@lunn.ch> <20201031143215.GA1076434@lunn.ch> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201031143215.GA1076434@lunn.ch> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Oct 31, 2020 at 03:32:15PM +0100, Andrew Lunn wrote: > > Sure, I just wanted to add the comment before others simply copy and > > paste this (pseudo) code. And in patch 9 (aquantia) and 18 (realtek) > > it is used as is. And IIRC at least the Aquantia PHY doesn't mask > > the interrupt status. > > And that is were we are going to have issues with this patch set, and > need review by individual PHY driver maintainers, or a good look at > the datasheet. > Yep, I already started to comb through all the drivers and their datasheets so that I can only check for the interrupts that the driver enables. Ioana