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[23.128.96.18]) by mx.google.com with ESMTP id bd20si3380488edb.98.2020.11.02.10.25.27; Mon, 02 Nov 2020 10:25:50 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725929AbgKBSXE (ORCPT + 99 others); Mon, 2 Nov 2020 13:23:04 -0500 Received: from foss.arm.com ([217.140.110.172]:35954 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725797AbgKBSXD (ORCPT ); Mon, 2 Nov 2020 13:23:03 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D5339139F; Mon, 2 Nov 2020 10:23:02 -0800 (PST) Received: from [10.57.54.223] (unknown [10.57.54.223]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 03F0E3F719; Mon, 2 Nov 2020 10:22:59 -0800 (PST) Subject: Re: [PATCH v18 3/4] dt-bindings: arm-smmu: Add compatible string for Adreno GPU SMMU To: Jordan Crouse , linux-arm-msm@vger.kernel.org Cc: iommu@lists.linux-foundation.org, Will Deacon , Rob Herring , Rob Clark , Bjorn Andersson , Joerg Roedel , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20201102171416.654337-1-jcrouse@codeaurora.org> <20201102171416.654337-4-jcrouse@codeaurora.org> From: Robin Murphy Message-ID: <77278507-a6be-8517-6f76-02a0ff588e39@arm.com> Date: Mon, 2 Nov 2020 18:22:58 +0000 User-Agent: Mozilla/5.0 (Windows NT 10.0; rv:78.0) Gecko/20100101 Thunderbird/78.4.0 MIME-Version: 1.0 In-Reply-To: <20201102171416.654337-4-jcrouse@codeaurora.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2020-11-02 17:14, Jordan Crouse wrote: > Every Qcom Adreno GPU has an embedded SMMU for its own use. These > devices depend on unique features such as split pagetables, > different stall/halt requirements and other settings. Identify them > with a compatible string so that they can be identified in the > arm-smmu implementation specific code. > > Signed-off-by: Jordan Crouse > Reviewed-by: Rob Herring > Signed-off-by: Rob Clark > Reviewed-by: Bjorn Andersson > --- > > Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > index 503160a7b9a0..3b63f2ae24db 100644 > --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > @@ -28,8 +28,6 @@ properties: > - enum: > - qcom,msm8996-smmu-v2 > - qcom,msm8998-smmu-v2 > - - qcom,sc7180-smmu-v2 > - - qcom,sdm845-smmu-v2 What about the "Apps SMMU" instances? Those are distinct and don't have/need the GPU special behaviour, right? Robin. > - const: qcom,smmu-v2 > > - description: Qcom SoCs implementing "arm,mmu-500" > @@ -40,6 +38,13 @@ properties: > - qcom,sm8150-smmu-500 > - qcom,sm8250-smmu-500 > - const: arm,mmu-500 > + - description: Qcom Adreno GPUs implementing "arm,smmu-v2" > + items: > + - enum: > + - qcom,sc7180-smmu-v2 > + - qcom,sdm845-smmu-v2 > + - const: qcom,adreno-smmu > + - const: qcom,smmu-v2 > - description: Marvell SoCs implementing "arm,mmu-500" > items: > - const: marvell,ap806-smmu-500 >