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Date:   Mon, 2 Nov 2020 14:46:33 -0700
From:   Mathieu Poirier <mathieu.poirier@linaro.org>
To:     Suzuki K Poulose <suzuki.poulose@arm.com>
Cc:     linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org,
        coresight@lists.linaro.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 06/26] coresight: etm4x: Handle access to TRCSSPCICRn
Message-ID: <20201102214633.GD2749502@xps15>
References: <20201028220945.3826358-1-suzuki.poulose@arm.com>
 <20201028220945.3826358-8-suzuki.poulose@arm.com>
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In-Reply-To: <20201028220945.3826358-8-suzuki.poulose@arm.com>
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Hi Suzuki,

On Wed, Oct 28, 2020 at 10:09:25PM +0000, Suzuki K Poulose wrote:
> TRCSSPCICR<n> is present only if all of the following are true:
> 	TRCIDR4.NUMSSCC > n.
> 	TRCIDR4.NUMPC > 0b0000 .
> 	TRCSSCSR<n>.PC == 0b1
> 
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-etm4x-core.c | 13 ++++++++-----
>  1 file changed, 8 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index d78a37b6592c..0310eac9dc16 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -175,8 +175,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
>  			       drvdata->base + TRCSSCCRn(i));
>  		writel_relaxed(config->ss_status[i],
>  			       drvdata->base + TRCSSCSRn(i));
> -		writel_relaxed(config->ss_pe_cmp[i],
> -			       drvdata->base + TRCSSPCICRn(i));
> +		if (drvdata->nr_pe)

Aren't you missing to check the value of the PC bit in TRCSSCSRn?

                /*
                 * TRCSSCSRn:PC, bit[3]: Indidate support for single-shot PE
                 * comparator input.
                 */
                if (drvdata->nr_pe && (config->ss_status[i] & BIT(3)))


I have picked up patches 1 to 5 and added a "Cc:stable" to paches 2, 4 and 5.
More comments to come tomorrow.


Thanks,
Mathieu

> +			writel_relaxed(config->ss_pe_cmp[i],
> +				       drvdata->base + TRCSSPCICRn(i));
>  	}
>  	for (i = 0; i < drvdata->nr_addr_cmp; i++) {
>  		writeq_relaxed(config->addr_val[i],
> @@ -1228,7 +1229,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
>  	for (i = 0; i < drvdata->nr_ss_cmp; i++) {
>  		state->trcssccr[i] = readl(drvdata->base + TRCSSCCRn(i));
>  		state->trcsscsr[i] = readl(drvdata->base + TRCSSCSRn(i));
> -		state->trcsspcicr[i] = readl(drvdata->base + TRCSSPCICRn(i));
> +		if (drvdata->nr_pe)
> +			state->trcsspcicr[i] = readl(drvdata->base + TRCSSPCICRn(i));
>  	}
>  
>  	for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
> @@ -1344,8 +1346,9 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
>  			       drvdata->base + TRCSSCCRn(i));
>  		writel_relaxed(state->trcsscsr[i],
>  			       drvdata->base + TRCSSCSRn(i));
> -		writel_relaxed(state->trcsspcicr[i],
> -			       drvdata->base + TRCSSPCICRn(i));
> +		if (drvdata->nr_pe)
> +			writel_relaxed(state->trcsspcicr[i],
> +				       drvdata->base + TRCSSPCICRn(i));
>  	}
>  
>  	for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
> -- 
> 2.24.1
>