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[23.128.96.18]) by mx.google.com with ESMTP id k5si1972991ejk.655.2020.11.02.23.58.23; Mon, 02 Nov 2020 23:58:46 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727927AbgKCH5C (ORCPT + 99 others); Tue, 3 Nov 2020 02:57:02 -0500 Received: from mga07.intel.com ([134.134.136.100]:7630 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727567AbgKCH5B (ORCPT ); Tue, 3 Nov 2020 02:57:01 -0500 IronPort-SDR: bf6FIkVNlVPNWpONvz/fLf1Fuy2H6biIrnk2LCucLoUll5RBauDK9n2z2pK43qeMzAtwcjrVUQ MLT3OnjCs0yg== X-IronPort-AV: E=McAfee;i="6000,8403,9793"; a="233183363" X-IronPort-AV: E=Sophos;i="5.77,447,1596524400"; d="scan'208";a="233183363" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2020 23:57:01 -0800 IronPort-SDR: vRrAit4sJJp4SKMMfiUJ3uFdVuX9DHmv0vKYy38mjSIoFpr2RT+DTPQl3hMsQuochB12ZICItq n0dKaPviluPA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,447,1596524400"; d="scan'208";a="336416497" Received: from sgsxdev004.isng.intel.com (HELO localhost) ([10.226.88.13]) by orsmga002.jf.intel.com with ESMTP; 02 Nov 2020 23:56:57 -0800 From: "Ramuthevar,Vadivel MuruganX" To: miquel.raynal@bootlin.com, vigneshr@ti.com, tudor.ambarus@microchip.com, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, simon.k.r.goldschmidt@gmail.com, dinguyen@kernel.org, richard@nod.at, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, "Ramuthevar,Vadivel MuruganX" Subject: [PATCH v16 0/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC Date: Tue, 3 Nov 2020 15:56:53 +0800 Message-Id: <20201103075655.18699-1-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.11.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds the new IP of Nand Flash Controller(NFC) support on Intel's Lightning Mountain(LGM) SoC. DMA is used for burst data transfer operation, also DMA HW supports aligned 32bit memory address and aligned data access by default. DMA burst of 8 supported. Data register used to support the read/write operation from/to device. NAND controller also supports in-built HW ECC engine. NAND controller driver implements ->exec_op() to replace legacy hooks, these specific call-back method to execute NAND operations. Thanks Miquel, Boris, Andy, Arnd and Rob for the review comments and suggestions. --- v16: - address Miquel Raynal review comments update - modify the commit message - add unit for timeout_ms variable - insert nand_sdr_timings directly in the function instead of adding helper function. - modify the code to handle single CS in probe - replace 'reg' property instead of 'nand,cs' - add 2 compatible strings generic one followed by intel,lgm-ebunand Resend-v15: - Rebased to mtd/for-5.10 v15: - Address Miquel review comments update - add common helper function for status check for ebu_nand_waitrdy() v14: - Address Andy's review comments - align the headers and revome Duplicates - replcace numerical const values by HZ_PER_MHZ and USEC_PER_SEC defined macros - add dev_err_probe() api instead of legacy err check - add get_unaligned_le32() api instead of manual endiness - remove redudent check - split the lines logically in between and add require spaces v13: - Address Miquel Raynal review comments - update the return type with variable 'ret' - handle err check statement properly - change the naming convention aligned with recently changed the naming around the data interface data structure and function names - replace by div 8 instead of <<4 in ecc calculation better code readability - handle check_only properly like existing drivers v12-resend: - No Change v12: - address Miquel Raynal review comments update - add/modify the comments for better understanding - handle the check_only variable - update the ecc function based on the existing drivers - add newline - verify that mtd->name is set after nand_set_flash_node() - add the check WARN_ON(ret); v11-resend: - Rebase to v5.8-rc1 v11: - No Change v10: - No Change v9: - No change v8: - fix the kbuild bot warnings - correct the typo's v7: - indentation issue is fixed - add error check for retrieve the resource from dt v6: - update EBU_ADDR_SELx register base value build it from DT - Add tabs in in Kconfig v5: - replace by 'HSNAND_CLE_OFFS | HSNAND_CS_OFFS' to NAND_WRITE_CMD and NAND_WRITE_ADDR - remove the unused macros - update EBU_ADDR_MASK(x) macro - update the EBU_ADDR_SELx register values to be written v4: - add ebu_nand_cs structure for multiple-CS support - mask/offset encoding for 0x51 value - update macro HSNAND_CTL_ENABLE_ECC - drop the op argument and un-used macros. - updated the datatype and macros - add function disable nand module - remove ebu_host->dma_rx = NULL; - rename MMIO address range variables to ebu and hsnand - implement ->setup_data_interface() - update label err_cleanup_nand and err_cleanup_dma - add return value check in the nand_remove function - add/remove tabs and spaces as per coding standard - encoded CS ids by reg property v3: - Add depends on MACRO in Kconfig - file name update in Makefile - file name update to intel-nand-controller - modification of MACRO divided like EBU, HSNAND and NAND - add NAND_ALE_OFFS, NAND_CLE_OFFS and NAND_CS_OFFS - rename lgm_ to ebu_ and _va suffix is removed in the whole file - rename structure and varaibles as per review comments. - remove lgm_read_byte(), lgm_dev_ready() and cmd_ctrl() un-used function - update in exec_op() as per review comments - rename function lgm_dma_exit() by lgm_dma_cleanup() - hardcoded magic value for base and offset replaced by MACRO defined - mtd_device_unregister() + nand_cleanup() instead of nand_release() v2: - implement the ->exec_op() to replaces the legacy hook-up. - update the commit message - add MIPS maintainers and xway_nand driver author in CC v1: - initial version dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC --- v16: - No change resend-v15: - No change v15: - No change v14: - No change v13: - No change v12-Resend: - No Change v12: - No change v11-resend: - No change v11: - Fixed the compatible issue with example 10: - fix bot errors v9: - Rob's review comments address - dual licensed - compatible change - add reg-names - drop clock-names and clock-cells - correct typo's v8: No change v7: - Rob's review comments addressed - dt-schema build issue fixed with upgraded dt-schema v6: - Rob's review comments addressed in YAML file - add addr_sel0 and addr_sel1 reg-names in YAML example v5: - add the example in YAML file v4: - No change v3: - No change v2: YAML compatible string update to intel, lgm-nand-controller v1: - initial version Ramuthevar Vadivel Murugan (2): dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC mtd: rawnand: Add NAND controller support on Intel LGM SoC .../devicetree/bindings/mtd/intel,lgm-nand.yaml | 99 +++ drivers/mtd/nand/raw/Kconfig | 8 + drivers/mtd/nand/raw/Makefile | 1 + drivers/mtd/nand/raw/intel-nand-controller.c | 722 +++++++++++++++++++++ 4 files changed, 830 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml create mode 100644 drivers/mtd/nand/raw/intel-nand-controller.c -- 2.11.0