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Date:   Wed, 4 Nov 2020 11:35:31 +0100
From:   Wolfram Sang <wsa@kernel.org>
To:     Michael.Wu@vatics.com
Cc:     jarkko.nikula@linux.intel.com, andriy.shevchenko@linux.intel.com,
        mika.westerberg@linux.intel.com, linux-i2c@vger.kernel.org,
        linux-kernel@vger.kernel.org, morgan.chang@vatics.com
Subject: Re: [PATCH 2/2] i2c: designware: slave should do WRITE_REQUESTED
 before WRITE_RECEIVED
Message-ID: <20201104103531.GA3984@ninjato>
References: <20201030080420.28016-1-michael.wu@vatics.com>
 <20201030080420.28016-3-michael.wu@vatics.com>
 <20201103210349.GE1583@kunai>
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> Not exactly. There're an interrupt state name "RD_REQ" but no one named
> like "WR_REQ".
>=20
> For read-request, the slave will get a RD_REQ interrupt.=20
> For write-request, the slave won't be interrupted until data arrived to
> trigger interrupt "RX_FULL".
>=20
> I tried to use GPIO to simulate an I2C master. I only sent its own
> address + W bit without any data and then I got only a STOP_DET interrupt.
> If I sent its own address + W bit + one byte data and then I got one
> RX_FULL and a STOP_DET.
>=20
> It seems the controller doesn't interrupt when RW bit is W, but R does.

Thanks for the detailed explanation! Okay, then what you do looks
correct to me (from a high level perspective without really knowing the
HW): when RX is full, you first send the state WRITE_REQUESTED when
there is no other transfer on-going. Then you send WRITE_RECEIVED
immediately. I think this is the way to do it.


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