Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
MIME-Version: 1.0
References: <CGME20201104103726eucas1p248b51b25f5ee42898bf03e9cb2229c5d@eucas1p2.samsung.com>
 <20201104103657.18007-1-s.nawrocki@samsung.com> <20201104103657.18007-6-s.nawrocki@samsung.com>
In-Reply-To: <20201104103657.18007-6-s.nawrocki@samsung.com>
Reply-To: cwchoi00@gmail.com
From:   Chanwoo Choi <cwchoi00@gmail.com>
Date:   Wed, 4 Nov 2020 21:31:08 +0900
Message-ID: <CAGTfZH2uSYesGdOikGZ_2qBWe4i+yZ6RnczJyn5ML=pvusC+iw@mail.gmail.com>
Subject: Re: [PATCH v8 5/7] ARM: dts: exynos: Add interconnect properties to
 Exynos4412 bus nodes
To:     Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc:     Georgi Djakov <georgi.djakov@linaro.org>,
        Chanwoo Choi <cw00.choi@samsung.com>,
        Krzysztof Kozlowski <krzk@kernel.org>,
        devicetree <devicetree@vger.kernel.org>,
        linux-samsung-soc <linux-samsung-soc@vger.kernel.org>,
        Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>,
        Linux PM list <linux-pm@vger.kernel.org>,
        Seung-Woo Kim <sw0312.kim@samsung.com>,
        =?UTF-8?B?QXJ0dXIgxZp3aWdvxYQ=?= <a.swigon@samsung.com>,
        Rob Herring <robh+dt@kernel.org>,
        linux-kernel <linux-kernel@vger.kernel.org>,
        MyungJoo Ham <myungjoo.ham@samsung.com>,
        dri-devel <dri-devel@lists.freedesktop.org>,
        linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
        Marek Szyprowski <m.szyprowski@samsung.com>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
Precedence: bulk

Hi Sylwester,

On Wed, Nov 4, 2020 at 7:37 PM Sylwester Nawrocki
<s.nawrocki@samsung.com> wrote:
>
> This patch adds the following properties for Exynos4412 interconnect
> bus nodes:
>  - interconnects: to declare connections between nodes in order to
>    guarantee PM QoS requirements between nodes,
>  - #interconnect-cells: required by the interconnect framework,
>  - samsung,data-clk-ratio: which allows to specify minimum data clock
>    frequency corresponding to requested bandwidth for each bus.
>
> Note that #interconnect-cells is always zero and node IDs are not
> hardcoded anywhere.
>
> Signed-off-by: Artur =C5=9Awigo=C5=84 <a.swigon@samsung.com>
> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> ---
> Changes for v8:
>  - none.
>
> Changes for v7:
>  - adjusted to the DT property changes: "interconnects" instead
>    of "samsung,interconnect-parent", "samsung,data-clk-ratio"
>    instead of "bus-width".
>
> Changes for v6:
>  - added bus-width property in bus_dmc node.
>
> Changes for v5:
>  - adjust to renamed exynos,interconnect-parent-node property,
>  - add properties in common exynos4412.dtsi file rather than
>    in Odroid specific odroid4412-odroid-common.dtsi.
> ---
>  arch/arm/boot/dts/exynos4412.dtsi | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos=
4412.dtsi
> index e76881d..4999e68 100644
> --- a/arch/arm/boot/dts/exynos4412.dtsi
> +++ b/arch/arm/boot/dts/exynos4412.dtsi
> @@ -383,6 +383,8 @@
>                         clocks =3D <&clock CLK_DIV_DMC>;
>                         clock-names =3D "bus";
>                         operating-points-v2 =3D <&bus_dmc_opp_table>;
> +                       samsung,data-clock-ratio =3D <4>;
> +                       #interconnect-cells =3D <0>;
>                         status =3D "disabled";
>                 };
>
> @@ -452,6 +454,8 @@
>                         clocks =3D <&clock CLK_DIV_GDL>;
>                         clock-names =3D "bus";
>                         operating-points-v2 =3D <&bus_leftbus_opp_table>;
> +                       interconnects =3D <&bus_dmc>;
> +                       #interconnect-cells =3D <0>;
>                         status =3D "disabled";
>                 };
>
> @@ -468,6 +472,8 @@
>                         clocks =3D <&clock CLK_ACLK160>;
>                         clock-names =3D "bus";
>                         operating-points-v2 =3D <&bus_display_opp_table>;
> +                       interconnects =3D <&bus_leftbus &bus_dmc>;
> +                       #interconnect-cells =3D <0>;
>                         status =3D "disabled";
>                 };
>
> --
> 2.7.4
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>

--=20
Best Regards,
Chanwoo Choi