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[23.128.96.18]) by mx.google.com with ESMTP id v6si1176592edt.456.2020.11.04.04.40.29; Wed, 04 Nov 2020 04:40:51 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vHCesrKk; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729944AbgKDMig (ORCPT + 99 others); Wed, 4 Nov 2020 07:38:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729826AbgKDMif (ORCPT ); Wed, 4 Nov 2020 07:38:35 -0500 Received: from mail-vs1-xe44.google.com (mail-vs1-xe44.google.com [IPv6:2607:f8b0:4864:20::e44]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 221C1C0613D3 for ; Wed, 4 Nov 2020 04:38:35 -0800 (PST) Received: by mail-vs1-xe44.google.com with SMTP id b3so11376465vsc.5 for ; Wed, 04 Nov 2020 04:38:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=/S4zGDHNvBcp/JjgO0AP61FUw/3vZ8bf/zKjIqYowfM=; b=vHCesrKkyHuFBvBeiM0yHWA+EJXvJsNfwNNvS2zTDIQrNEwlw3Ae/ItTrhNJzVlLHY BjM0AIP3d1wusAoesybRXeCqwWh6Vso6Tm44LiCcMH6wOahcJ+XULMwFSkRQNm3x79Lz rCirFMmYpKQACmIkW3C8JZiuF2dnGEfr1vTZmimO6cxceADjfzqC1jWdPJG/nTu2Lox+ SPkCLevAADmcss77zcfJf0dXzUePyRP+ECqj/2c2vIiGAXmMQ1plnEk4s7xzEp3zy4Es 3QnxVlGMAWLL5d+CHHwmi6TdrqLsOYqY3M4u6QyR4ZoZaxIoAB4uh8qBnfXOV9FY3EmB mstQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=/S4zGDHNvBcp/JjgO0AP61FUw/3vZ8bf/zKjIqYowfM=; b=sP5UKg1Wt6sQVuU/zbDpuqXJXPXZ9S0Ea/C6nvsEhAyP+ixKTzIkaSmmR/snkFvk5k yC+uLyQTWonC0EwttOzHx8kjrrZtKmiKmbYIjmz8DYdLkquXT+P3gvl4cclqQHn4oZVs 832VCOjbyMFRStamB/KdWvWZEgjrXRbKX/IFQFHOmi8rOQFsdHUG6mKJjSoxachtbwjl FjMC3orgoWj79MluQ8AQ3D8PiiD5Q5kmc/g9wXr/ZJQy4SyJ0vhZ6vuqXvAs9ajKsFac UXO6BpwGT9+xD8qnVhal59Gf6Uaq0GTuU0JRYrsVsNBfWjEs+82XAJOtKJ7KF6JYvObt nc5Q== X-Gm-Message-State: AOAM5339HdrX63pkXBqcKf1+kzLCIZO3JpJL47gnJizfQMBSUWJZWDOL J5sLrbQ7C+lMWzrZjZUTRmrBMTuckbta2vEUZUoFRQ== X-Received: by 2002:a67:ec9a:: with SMTP id h26mr21851524vsp.34.1604493514271; Wed, 04 Nov 2020 04:38:34 -0800 (PST) MIME-Version: 1.0 References: <1604397269-2780-1-git-send-email-rui_feng@realsil.com.cn> In-Reply-To: <1604397269-2780-1-git-send-email-rui_feng@realsil.com.cn> From: Ulf Hansson Date: Wed, 4 Nov 2020 13:37:57 +0100 Message-ID: Subject: Re: [PATCH 1/8] mmc: rtsx: Add test mode for RTS5261 To: Rui Feng , Greg Kroah-Hartman Cc: Arnd Bergmann , Linux Kernel Mailing List , "linux-mmc@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 3 Nov 2020 at 10:54, wrote: > > From: Rui Feng > > This patch add test mode for RTS5261. > If test mode is set, reader will switch to SD Express mode > mandatorily, and this mode is used by factory testing only. > > Signed-off-by: Rui Feng Greg, It seems this series is best funneld via my mmc tree, due to dependency to recent changes I have queued. I am fine to pick this as well, but awaiting an ack from you before I go ahead. Kind regards Uffe > --- > drivers/misc/cardreader/rts5261.h | 5 ----- > drivers/mmc/host/rtsx_pci_sdmmc.c | 19 ++++++++++++++++--- > include/linux/rtsx_pci.h | 4 ++++ > 3 files changed, 20 insertions(+), 8 deletions(-) > > diff --git a/drivers/misc/cardreader/rts5261.h b/drivers/misc/cardreader/rts5261.h > index 8d80f0d5d5d6..80179353bc46 100644 > --- a/drivers/misc/cardreader/rts5261.h > +++ b/drivers/misc/cardreader/rts5261.h > @@ -60,11 +60,6 @@ > /* DMACTL 0xFE2C */ > #define RTS5261_DMA_PACK_SIZE_MASK 0xF0 > > -/* FW config info register */ > -#define RTS5261_FW_CFG_INFO0 0xFF50 > -#define RTS5261_FW_EXPRESS_TEST_MASK (0x01<<0) > -#define RTS5261_FW_EA_MODE_MASK (0x01<<5) > - > /* FW status register */ > #define RTS5261_FW_STATUS 0xFF56 > #define RTS5261_EXPRESS_LINK_FAIL_MASK (0x01<<7) > diff --git a/drivers/mmc/host/rtsx_pci_sdmmc.c b/drivers/mmc/host/rtsx_pci_sdmmc.c > index c453ad403aa8..26be11a096cb 100644 > --- a/drivers/mmc/host/rtsx_pci_sdmmc.c > +++ b/drivers/mmc/host/rtsx_pci_sdmmc.c > @@ -47,6 +47,8 @@ struct realtek_pci_sdmmc { > bool using_cookie; > }; > > +static int sdmmc_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios); > + > static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host) > { > return &(host->pdev->dev); > @@ -898,6 +900,7 @@ static int sd_power_on(struct realtek_pci_sdmmc *host) > struct mmc_host *mmc = host->mmc; > int err; > u32 val; > + u8 test_mode; > > if (host->power_state == SDMMC_POWER_ON) > return 0; > @@ -925,6 +928,15 @@ static int sd_power_on(struct realtek_pci_sdmmc *host) > return err; > > if (PCI_PID(pcr) == PID_5261) { > + /* > + * If test mode is set switch to SD Express mandatorily, > + * this is only for factory testing. > + */ > + rtsx_pci_read_register(pcr, RTS5261_FW_CFG_INFO0, &test_mode); > + if (test_mode & RTS5261_FW_EXPRESS_TEST_MASK) { > + sdmmc_init_sd_express(mmc, NULL); > + return 0; > + } > if (pcr->extra_caps & EXTRA_CAPS_SD_EXPRESS) > mmc->caps2 |= MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V; > /* > @@ -1354,11 +1366,12 @@ static int sdmmc_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios) > RTS5261_AUX_CLK_16M_EN, RTS5261_AUX_CLK_16M_EN); > rtsx_pci_write_register(pcr, RTS5261_FW_CFG0, > RTS5261_FW_ENTER_EXPRESS, RTS5261_FW_ENTER_EXPRESS); > + rtsx_pci_write_register(pcr, RTS5261_FW_CFG1, > + RTS5261_MCU_CLOCK_GATING, RTS5261_MCU_CLOCK_GATING); > rtsx_pci_write_register(pcr, RTS5261_FW_CFG1, > RTS5261_MCU_BUS_SEL_MASK | RTS5261_MCU_CLOCK_SEL_MASK > - | RTS5261_MCU_CLOCK_GATING | RTS5261_DRIVER_ENABLE_FW, > - RTS5261_MCU_CLOCK_SEL_16M | RTS5261_MCU_CLOCK_GATING > - | RTS5261_DRIVER_ENABLE_FW); > + | RTS5261_DRIVER_ENABLE_FW, > + RTS5261_MCU_CLOCK_SEL_16M | RTS5261_DRIVER_ENABLE_FW); > host->eject = true; > return 0; > } > diff --git a/include/linux/rtsx_pci.h b/include/linux/rtsx_pci.h > index b47959f48ccd..db249e8707f3 100644 > --- a/include/linux/rtsx_pci.h > +++ b/include/linux/rtsx_pci.h > @@ -658,6 +658,10 @@ > #define PM_WAKE_EN 0x01 > #define PM_CTRL4 0xFF47 > > +/* FW config info register */ > +#define RTS5261_FW_CFG_INFO0 0xFF50 > +#define RTS5261_FW_EXPRESS_TEST_MASK (0x01 << 0) > +#define RTS5261_FW_EA_MODE_MASK (0x01 << 5) > #define RTS5261_FW_CFG0 0xFF54 > #define RTS5261_FW_ENTER_EXPRESS (0x01 << 0) > > -- > 2.17.1 >