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Date:   Wed, 4 Nov 2020 13:06:37 +0000
From:   Mark Rutland <mark.rutland@arm.com>
To:     Marco Elver <elver@google.com>
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Subject: Re: [PATCH v7 3/9] arm64, kfence: enable KFENCE for ARM64
Message-ID: <20201104130111.GA7577@C02TD0UTHF1T.local>
References: <20201103175841.3495947-1-elver@google.com>
 <20201103175841.3495947-4-elver@google.com>
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On Tue, Nov 03, 2020 at 06:58:35PM +0100, Marco Elver wrote:
> Add architecture specific implementation details for KFENCE and enable
> KFENCE for the arm64 architecture. In particular, this implements the
> required interface in <asm/kfence.h>.
> 
> KFENCE requires that attributes for pages from its memory pool can
> individually be set. Therefore, force the entire linear map to be mapped
> at page granularity. Doing so may result in extra memory allocated for
> page tables in case rodata=full is not set; however, currently
> CONFIG_RODATA_FULL_DEFAULT_ENABLED=y is the default, and the common case
> is therefore not affected by this change.
> 
> Reviewed-by: Dmitry Vyukov <dvyukov@google.com>
> Co-developed-by: Alexander Potapenko <glider@google.com>
> Signed-off-by: Alexander Potapenko <glider@google.com>
> Signed-off-by: Marco Elver <elver@google.com>

Thanks for dilligently handling all the review feedback. This looks good
to me now, so FWIW:

Reviewed-by: Mark Rutland <mark.rutland@arm.com>

There is one thing that I thing we should improve as a subsequent
cleanup, but I don't think that should block this as-is.

> +#define KFENCE_SKIP_ARCH_FAULT_HANDLER "el1_sync"

IIUC, the core kfence code is using this to figure out where to trace
from when there's a fault taken on an access to a protected page.

It would be better if the arch code passed the exception's pt_regs into
the kfence fault handler, and the kfence began the trace began from
there. That would also allow for dumping the exception registers which
can help with debugging (e.g. figuring out how the address was derived
when it's calculated from multiple source registers). That would also be
a bit more robust to changes in an architectures' exception handling
code.

Thanks,
Mark.