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[23.128.96.18]) by mx.google.com with ESMTP id e2si89834ejq.58.2020.11.04.17.55.34; Wed, 04 Nov 2020 17:55:58 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=SaylY8xY; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730435AbgKDTyy (ORCPT + 99 others); Wed, 4 Nov 2020 14:54:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40432 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730386AbgKDTyy (ORCPT ); Wed, 4 Nov 2020 14:54:54 -0500 Received: from mail-ed1-x544.google.com (mail-ed1-x544.google.com [IPv6:2a00:1450:4864:20::544]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C370EC0613D3 for ; Wed, 4 Nov 2020 11:54:53 -0800 (PST) Received: by mail-ed1-x544.google.com with SMTP id w1so22629709edv.11 for ; Wed, 04 Nov 2020 11:54:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=wYADTYJrthOK2FgDOSfisjNfho6lkFoYFvTmRS3AF6o=; b=SaylY8xYIN/kn6pp6vqgZKWFPI3aMZEDuGl40Neby3UAsh/OdwbL/BOL6VIMd1xr54 u1lN0DgFxGMEutrFHArJ0+jAUUmRPp+XeZlWdBtTzx09tswaSsx7r/lNGnGT2jBgUTok zbibiQOU8l2pYWkCZ1XrGFaXIxEfntBR1qvWs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=wYADTYJrthOK2FgDOSfisjNfho6lkFoYFvTmRS3AF6o=; b=Ezx63CpbvJxHytxOuDB8mqPUrTPQWS9mu/IqBhL9j7I8iWx/uMjNexkmn/NVpvf8UJ 6d5nb/i0XZq9FRSJry9+4kl89UPs/Fx2sSgEUlVyQRKFRR8j6v1L+qScNQ+31u5Zksdt EonVbQKds4kOz9KCIgGTwvS++0QmTgSi2WngrjlyU5S7zh6iQRSYIjMCtu0/hGY28hUD HL/EbH0yCgOFu/u7OPL7S8/CuOP64i+oahrYiUEFlyrsJlGoPNbqnJMz+41u1nSE6pC3 9u7ySR91EDNy8fnz3WvzVMLzsl2CJ8tPZiCz2IqxBw77eleCfNh36STxAmZYKDw6gZ0K k3/w== X-Gm-Message-State: AOAM532Ad8e3wf2ja95PACsBrfsMJBfSa3lBgZbjhAcnt5H7Wkd060gm T6ZzPB4M0MVeufSH8Xz8gcdPg3RvJdCp8FDtlzs21Q== X-Received: by 2002:a05:6402:4c6:: with SMTP id n6mr29304524edw.204.1604519692471; Wed, 04 Nov 2020 11:54:52 -0800 (PST) MIME-Version: 1.0 References: <20200929083217.25406-1-jagan@amarulasolutions.com> In-Reply-To: From: Jagan Teki Date: Thu, 5 Nov 2020 01:24:40 +0530 Message-ID: Subject: Re: [PATCH v4 0/7] arm64: dts: rockchip: Add Engicam PX30.Core To: Heiko Stuebner , Rob Herring Cc: Suniel Mahesh , Michael Trimarchi , linux-arm-kernel , "open list:ARM/Rockchip SoC..." , devicetree , linux-kernel , linux-amarula Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Oct 22, 2020 at 12:27 AM Jagan Teki wrote: > > Hi Heiko, > > On Tue, Sep 29, 2020 at 2:02 PM Jagan Teki wrote: > > > > PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. > > > > PX30.Core needs to mount on top of Engicam baseboards for creating > > complete platform boards. > > > > Possible baseboards are, > > - EDIMM2.2 Starter Kit > > - C.TOUCH 2.0 Carrier Board > > > > Changes for v4: > > - collect Rob A-b > > Changes for v3: > > - resolved Johan comments about sorting node properties > > - add copyright to Amarula Solutions > > - update px30 dtsi author > > Changes for v2: > > - include C.TOUCH 2.0 carrier board > > - skip 10" OF LCD as it requires separate dts with panel support. > > > > Note: These baseboards can be used for i.MX8 SOM's as well. So having > > baseboard on respective SoC seems to be easy rather than making it > > common across all. > > > > Any inputs? > > Jagan. > > > > Jagan Teki (6): > > dt-bindings: arm: rockchip: Add Engicam PX30.Core EDIMM2.2 Starter Kit > > arm64: dts: rockchip: px30: Add Engicam EDIMM2.2 Starter Kit > > arm64: dts: rockchip: Add Engicam PX30.Core EDIMM2.2 Starter Kit > > dt-bindings: arm: rockchip: Add Engicam PX30.Core C.TOUCH 2.0 > > arm64: dts: rockchip: px30: Add Engicam C.TOUCH 2.0 > > arm64: dts: rockchip: Add Engicam PX30.Core C.TOUCH 2.0 > > > > Michael Trimarchi (1): > > arm64: dts: rockchip: Add Engicam PX30.Core SOM > > > > .../devicetree/bindings/arm/rockchip.yaml | 12 + > > arch/arm64/boot/dts/rockchip/Makefile | 2 + > > .../dts/rockchip/px30-engicam-common.dtsi | 39 +++ > > .../dts/rockchip/px30-engicam-ctouch2.dtsi | 8 + > > .../dts/rockchip/px30-engicam-edimm2.2.dtsi | 7 + > > .../dts/rockchip/px30-px30-core-ctouch2.dts | 22 ++ > > .../dts/rockchip/px30-px30-core-edimm2.2.dts | 21 ++ > > .../boot/dts/rockchip/px30-px30-core.dtsi | 232 ++++++++++++++++++ > > 8 files changed, 343 insertions(+) > > create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi > > create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi > > create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi > > create mode 100644 arch/arm64/boot/dts/rockchip/px30-px30-core-ctouch2.dts > > create mode 100644 arch/arm64/boot/dts/rockchip/px30-px30-core-edimm2.2.dts > > create mode 100644 arch/arm64/boot/dts/rockchip/px30-px30-core.dtsi > > Any further comments? Gentle ping.