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[23.128.96.18]) by mx.google.com with ESMTP id j15si668115ejb.160.2020.11.05.01.44.49; Thu, 05 Nov 2020 01:45:12 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vazstrmu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726729AbgKEJke (ORCPT + 99 others); Thu, 5 Nov 2020 04:40:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725308AbgKEJke (ORCPT ); Thu, 5 Nov 2020 04:40:34 -0500 Received: from mail-lf1-x143.google.com (mail-lf1-x143.google.com [IPv6:2a00:1450:4864:20::143]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F0836C0613CF for ; Thu, 5 Nov 2020 01:40:33 -0800 (PST) Received: by mail-lf1-x143.google.com with SMTP id l2so1364410lfk.0 for ; Thu, 05 Nov 2020 01:40:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=3hWsdnqZNjQDKpL2B785A/d5X3xt4A0wwW61OXRwY/c=; b=vazstrmuUGxShFcPSjK99UNszN8ebLO9vYsswJWPOI0ji007BIxdt1z8ZOgCPtgL0U 8fQ+lGVXy9yNBtPo6ecTCGNpM6ApZsTBHHdnJ8K78acvaIz7HvPnXP+fGAmNVv1/072v FzDEx07N1z7LiNMI50uDbiVBjR0upi+6Ch0pMOzuqWaqp5o0mZeoBaFBcJXGQ5AtgOGH vL2clxCTwdTJQvI79Ir21mh82m26V9sgmgn6fnvm611SmhTl/DFZiAT2XFhInpof2WZg VsLekC5EGBhggYbUYjBqVVL9zXyIIvOUBjU636//1r9gbQZHt6QM3GnOym2A0tBfXRFU 25OQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=3hWsdnqZNjQDKpL2B785A/d5X3xt4A0wwW61OXRwY/c=; b=hrq4ohUyqR+q12cnXtXk6qN2vi1JfyipI7mWPnQ/8SlqZMxYcVao95VupQWeDejdKo iL8PDhwCya7IvDPFTXKbXvhHhoDmI1t3cuI54ABC9DV53rf1sFjksjGcIYTaFqd3nJc9 zpDQ6JwIWdup6Ol9FRVw+i5lr1ZZlRxHkWlWBhq3QLbuK7+JiHP7j0lJGEg3LGuH8jTl OkJ9zO0nC4CSO3BnLFu3weaR+eT3L4ZGegHtVxk3fKeWRh1fDGyTM35tV5D6h+tPhLIg srHimxxsIY56P8+ufue3oK3auAuMlSu3JSi6tQJVt+t6Hn1aZ3pTazIOl4vzHSO8JXxc hwKg== X-Gm-Message-State: AOAM5315GXVvRr058b8BRM0yrOC6YpB3uxjQclFZbej1dmPR4en4kvEd C8R0QVHfv9Ga9Sc8EQDXeoYymeTh5Pac7wpdXJYPRzyFVI4d9A== X-Received: by 2002:a05:6512:3225:: with SMTP id f5mr605124lfe.441.1604569232429; Thu, 05 Nov 2020 01:40:32 -0800 (PST) MIME-Version: 1.0 References: <20201019141008.871177-1-daniel@0x0f.com> <20201019141008.871177-4-daniel@0x0f.com> In-Reply-To: <20201019141008.871177-4-daniel@0x0f.com> From: Linus Walleij Date: Thu, 5 Nov 2020 10:40:21 +0100 Message-ID: Subject: Re: [PATCH v2 3/5] gpio: msc313: MStar MSC313 GPIO driver To: Daniel Palmer , Marc Zyngier Cc: "open list:GPIO SUBSYSTEM" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , arm-kernel@lists.infradead.org, "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Oct 19, 2020 at 4:10 PM Daniel Palmer wrote: > This adds a driver that supports the GPIO block found in > MStar/SigmaStar ARMv7 SoCs. > > The controller seems to support 128 lines but where they > are wired up differs between chips and no currently known > chip uses anywhere near 128 lines so there needs to be some > per-chip data to collect together what lines actually have > physical pins attached and map the right names to them. > > The core peripherals seem to use the same lines on the > currently known chips but the lines used for the sensor > interface, lcd controller etc pins seem to be totally > different between the infinity and mercury chips > > The code tries to collect all of the re-usable names, > offsets etc together so that it's easy to build the extra > per-chip data for other chips in the future. > > So far this only supports the MSC313 and MSC313E chips. > > Support for the SSC8336N (mercury5) is trivial to add once > all of the lines have been mapped out. > > Signed-off-by: Daniel Palmer This looks really nice, the generic hierarchical IRQchip does its job very well here. I saw you would send another version but this already looks like merge material. Certainly any remaining issues can be ironed out in-tree. > +config GPIO_MSC313 > + bool "MStar MSC313 GPIO support" > + default y if ARCH_MSTARV7 > + depends on ARCH_MSTARV7 > + select GPIOLIB_IRQCHIP select IRQ_DOMAIN_HIERARCHY since you are dependent on this. (Else people will soon report problems with randconfig...) > +/* The parent interrupt controller needs the GIC interrupt type set to GIC_SPI > + * so we need to provide the fwspec. Essentially gpiochip_populate_parent_fwspec_twocell > + * that puts GIC_SPI into the first cell. > + */ > +static void *msc313_gpio_populate_parent_fwspec(struct gpio_chip *gc, > + unsigned int parent_hwirq, > + unsigned int parent_type) > +{ > + struct irq_fwspec *fwspec; > + > + fwspec = kmalloc(sizeof(*fwspec), GFP_KERNEL); > + if (!fwspec) > + return NULL; > + > + fwspec->fwnode = gc->irq.parent_domain->fwnode; > + fwspec->param_count = 3; > + fwspec->param[0] = GIC_SPI; > + fwspec->param[1] = parent_hwirq; > + fwspec->param[2] = parent_type; > + > + return fwspec; > +} Clever. Looping in Marc Z so he can say if this looks allright to him. > +static int msc313e_gpio_child_to_parent_hwirq(struct gpio_chip *chip, > + unsigned int child, > + unsigned int child_type, > + unsigned int *parent, > + unsigned int *parent_type) > +{ > + struct msc313_gpio *priv = gpiochip_get_data(chip); > + unsigned int offset = priv->gpio_data->offsets[child]; > + int ret = -EINVAL; > + > + /* only the spi0 pins have interrupts on the parent > + * on all of the known chips and so far they are all > + * mapped to the same place > + */ > + if (offset >= OFF_SPI0_CZ && offset <= OFF_SPI0_DO) { > + *parent_type = child_type; > + *parent = ((offset - OFF_SPI0_CZ) >> 2) + 28; > + ret = 0; > + } > + > + return ret; > +} Neat! > +static int msc313_gpio_probe(struct platform_device *pdev) > +{ > + const struct msc313_gpio_data *match_data; > + struct msc313_gpio *gpio; > + struct gpio_chip *gpiochip; > + struct gpio_irq_chip *gpioirqchip; > + struct resource *res; > + struct irq_domain *parent_domain; > + struct device_node *parent_node; > + int ret; > + > + match_data = of_device_get_match_data(&pdev->dev); There is a lot of referencing &pdev->dev. I would add a local variable like this: struct device *dev = &pdev->dev and replace all &pdev->dev with that. It will make the code more compact and easier to read. Yours, Linus Walleij