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[23.128.96.18]) by mx.google.com with ESMTP id a4si732210ejc.628.2020.11.05.02.25.53; Thu, 05 Nov 2020 02:26:16 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b=WZOBpgLZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=st.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727836AbgKEKYf (ORCPT + 99 others); Thu, 5 Nov 2020 05:24:35 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:1758 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725827AbgKEKYe (ORCPT ); Thu, 5 Nov 2020 05:24:34 -0500 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 0A5A7Eo7002618; Thu, 5 Nov 2020 11:24:24 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=STMicroelectronics; bh=B6IJmwbJTZgT+xrzc4UseGf48pMkH/ns5azftzshw2Y=; b=WZOBpgLZhv9QbbzaE4hAz5uLRBPPT+5m/wQjKpaC8JG7Nd93VC0GDltS+k0U7dzzxOli PnS1ZDI5huRLzeCIaupNXR8V5GkY7mrvxc7hyZfvDtnqmbYajinrsenffyHJRVVKFZ9L YIvHsqZdojxAkW8AhSESfho7ZEji8YIdCIywkBd+1rdCPuTUjEH12k1Q7th3CDRf1HsB DVmkPqD1wFeGtqLShL0kFOWSAyTAE4xz4kJXqSQRj20+buu8xVv9PRkDJ0i1lYwJ6ird WSKC7bR2CmrBcoGIUKyeFeAvMdFYAE79/bG8IOtkxndn8LgDvRvjNp9VImy2A014URpB OQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 34h031yynf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 05 Nov 2020 11:24:24 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C471F100034; Thu, 5 Nov 2020 11:24:23 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag3node2.st.com [10.75.127.8]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id B26C1238FDE; Thu, 5 Nov 2020 11:24:23 +0100 (CET) Received: from localhost (10.75.127.46) by SFHDAG3NODE2.st.com (10.75.127.8) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 5 Nov 2020 11:23:41 +0100 From: Lionel Debieve To: Alexandre Torgue , Maxime Coquelin , Rob Herring CC: , , , , Nicolas Toromanoff Subject: [PATCH 0/3] ARM: dts: stm32: enable crypto controllers Date: Thu, 5 Nov 2020 11:23:28 +0100 Message-ID: <20201105102331.12984-1-lionel.debieve@st.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG6NODE2.st.com (10.75.127.17) To SFHDAG3NODE2.st.com (10.75.127.8) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312,18.0.737 definitions=2020-11-05_05:2020-11-05,2020-11-05 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable the crypto controllers in the STM32MP157C-EV1 and STM32MP157A-DK1 STM32MP157C-DK2 boards. Lionel Debieve (2): ARM: dts: stm32: enable HASH by default on stm32mp15 ARM: dts: stm32: enable CRYP by default on stm32mp15 Nicolas Toromanoff (1): ARM: dts: stm32: enable CRC1 by default on stm32mp15 arch/arm/boot/dts/stm32mp157c-dk2.dts | 4 ++++ arch/arm/boot/dts/stm32mp157c-ed1.dts | 12 ++++++++++++ arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 8 ++++++++ 3 files changed, 24 insertions(+) -- 2.17.1