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From:   Shiju Jose <shiju.jose@huawei.com>
To:     <linux-edac@vger.kernel.org>, <linux-acpi@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <james.morse@arm.com>,
        <bp@alien8.de>, <tony.luck@intel.com>, <rjw@rjwysocki.net>,
        <lenb@kernel.org>, <rrichter@marvell.com>
CC:     <linuxarm@huawei.com>, <jonathan.cameron@huawei.com>,
        <shiju.jose@huawei.com>
Subject: [RFC PATCH 0/4] EDAC/ghes: Add EDAC device for recording the CPU error count
Date:   Thu, 5 Nov 2020 17:42:29 +0000
Message-ID: <20201105174233.1146-1-shiju.jose@huawei.com>
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For the firmware-first error handling on ARM64 hardware platforms,
CPU cache corrected error count is not recorded.
Create an CPU EDAC device and device blocks for the CPU caches
for this purpose. The EDAC device blocks  are created based on the
CPU caches information represented in the ACPI PPTT.

User-space application could monitor the recorded corrected error
count for the early fault detection.

Jonathan Cameron (1):
  ACPI: PPTT: Fix for a high level cache node detected in the low level

Shiju Jose (3):
  ACPI: PPTT: Add function acpi_find_cache_info
  EDAC/ghes: Add EDAC device for the CPU caches
  ACPI / APEI: Add reporting ARM64 CPU cache corrected error count

 drivers/acpi/apei/ghes.c  |  79 +++++++++++++++++++++-
 drivers/acpi/pptt.c       | 123 +++++++++++++++++++++++++++++++++-
 drivers/edac/Kconfig      |  10 +++
 drivers/edac/ghes_edac.c  | 135 ++++++++++++++++++++++++++++++++++++++
 include/acpi/ghes.h       |  27 ++++++++
 include/linux/cacheinfo.h |  12 ++++
 include/linux/cper.h      |   4 ++
 7 files changed, 386 insertions(+), 4 deletions(-)

-- 
2.17.1