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[76.210.143.223]) by smtp.gmail.com with ESMTPSA id i10sm3467604pjz.44.2020.11.05.18.02.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2020 18:02:58 -0800 (PST) Date: Thu, 05 Nov 2020 18:02:58 -0800 (PST) X-Google-Original-Date: Thu, 05 Nov 2020 18:02:56 PST (-0800) Subject: Re: [RFC PATCH] irqchip/sifive-plic: Fix getting wrong chip_data when interrupt is hierarchy In-Reply-To: <87y2jl81ft.fsf@nanos.tec.linutronix.de> CC: Marc Zyngier , jason@lakedaemon.net, geert+renesas@glider.be, greentime.hu@sifive.com, linux-kernel@vger.kernel.org, Atish Patra , linux-riscv@lists.infradead.org, Paul Walmsley , anup@brainfault.org, uli+renesas@fpond.eu, linux-renesas-soc@vger.kernel.org From: Palmer Dabbelt To: tglx@linutronix.de Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, 01 Nov 2020 08:52:06 PST (-0800), tglx@linutronix.de wrote: > On Sun, Nov 01 2020 at 12:10, Marc Zyngier wrote: > >> On Thu, 29 Oct 2020 10:37:38 +0800, Greentime Hu wrote: >>> This oops is caused by a wrong chip_data and it is because plic_irq_unmask >>> uses irq_get_chip_data(irq_data->irq) to get the chip_data. However it may >>> get another irq_data with the same irq_data->irq if it is hierarchy. >>> >>> In this case, it will get irq_data of sifive_gpio_irqchip instead of >>> plic_chip so that it will get a wrong chip_data and then the wrong lmask >>> of it to cause this oops. >>> >>> [...] >> >> Applied to irq/irqchip-next, thanks! > > That should go into urgent, the offending commit is in Linus tree already I agree. I'm assuming that's for Marc, but LMK if you guys want me to take it. Acked-by: Palmer Dabbelt Thanks!