Received: by 2002:a05:6a10:16a7:0:0:0:0 with SMTP id gp39csp1361252pxb; Fri, 6 Nov 2020 07:45:50 -0800 (PST) X-Google-Smtp-Source: ABdhPJx6xhDLPQfa7UDgjmq3R8gPYtpMLtTrwWA9wnFLaJc/yvI3YTHFxX3eZA8lVXzzIMHWWupd X-Received: by 2002:a50:baea:: with SMTP id x97mr2665083ede.81.1604677550035; Fri, 06 Nov 2020 07:45:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1604677550; cv=none; d=google.com; s=arc-20160816; b=cyLieiRpnInt+FiFhyUOEOjzEgk42SMYytVz4+LpXBAZ7xYH56/jVwGRkd2LccDqnr HxreMHrPl26HhUp4UHHOHTbvypbbqpYYEqlcW5J/dVO1WeTVa1Sndmbd1KsQcG3nE4de sbfidEcdw/p9edcCDFugT05UqDQ/jqVIB4kfgiGJqohuK0qnnII/9d2D8Nz+u+H5BqWF NdUboAwFkkRJJI48N8oxd4JdDXDGlpThOOMIqhZgRDSck2VHAwhlqfUyjeDKzhlO9GD2 rAfeDgAZy4bibLVPNekpPgzpz3vLxtPCEGghG4HZcqpdXMNh2IduCQBU4wRg2/bWFfzE IuiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:dkim-signature:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from; bh=kvzP1+o3QefuVm2M4WY6kUuSTHsekt98vQR+sG4CORw=; b=D49NHvCgvKkN5HOToCk10OjL6P6VNXP9o0BPkKi0S+fMcCI06WY4CmchxZYhO28LS8 FzoH+Tql3aAvJfZNEtoBrTGQGRdzG5xWR4iFlzptgi8+Xx+HRD0Yd1oylHbYcR4DP2x3 sPDq8g9c5K2qLhE3Rxn0C2ujgRo5bKqNMD7vjKyKDDBOg2ttJ6aVcaQxflmxR2vYDGSt nFRWFcc0fSXkqhVAMyEeRVI8WJ5ZhNvK5VxfdynVVWRSLyVf/twfKdqBhTJ5igkUJBo+ TKAczbvIHVZg2iJOWsEBndl4gU6DOmkFkgtbTghdCAhqHOgL4ODdvNh/zKDh4ENcNuKE BBcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=FMca3l3p; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id b6si1201995ejk.518.2020.11.06.07.45.27; Fri, 06 Nov 2020 07:45:50 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=FMca3l3p; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727709AbgKFPny (ORCPT + 99 others); Fri, 6 Nov 2020 10:43:54 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:3038 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727686AbgKFPnw (ORCPT ); Fri, 6 Nov 2020 10:43:52 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Fri, 06 Nov 2020 07:43:50 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 6 Nov 2020 15:43:52 +0000 Received: from audio.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Fri, 6 Nov 2020 15:43:48 +0000 From: Sameer Pujar To: , CC: , , , , , , , , , Sameer Pujar Subject: [PATCH v2 3/4] dt-bindings: interrupt-controller: arm,gic: Update Tegra compatibles Date: Fri, 6 Nov 2020 21:13:32 +0530 Message-ID: <1604677413-20411-4-git-send-email-spujar@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604677413-20411-1-git-send-email-spujar@nvidia.com> References: <1604677413-20411-1-git-send-email-spujar@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1604677430; bh=kvzP1+o3QefuVm2M4WY6kUuSTHsekt98vQR+sG4CORw=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:MIME-Version:Content-Type; b=FMca3l3pNloYrQFWl4hnLVQQijHf5bUTnCIfn7c8/xAbdMM558u7DSmUbUKA2KNx5 +UKl57wPuQi3fE+I2g3WaNVL0unx0+ExG0G1noIsIzTO51f6YCxboJo//9q4fgglvJ Rfs8K2fWoDgC8uLKGQqwj+2iMv/pJsYiZKON3ICN3QCiQ8hMseXaJ/DQYP5opEroQ0 Si5KfwKEPGXogovDk8PC/tbfZPnbv+KhD7Qjc7v2vb3iAzg2iFZ3pAXR4x5vY+3mXC wmXqT9mdpp4wbgmGYtgZBaALbvc/r0afCtLqlTEPvl/p5tWMRKmsLn5+35zYrqYdwD BiNUWcF1dVIUw== Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update Tegra compatibles to support newer Tegra chips and required combinations. Signed-off-by: Sameer Pujar Reviewed-by: Rob Herring --- .../devicetree/bindings/interrupt-controller/arm,gic.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml index 0688996..ba282f4 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml @@ -35,7 +35,6 @@ properties: - arm,gic-400 - arm,pl390 - arm,tc11mp-gic - - nvidia,tegra210-agic - qcom,msm-8660-qgic - qcom,msm-qgic2 @@ -53,6 +52,14 @@ properties: - const: brcm,brahma-b15-gic - const: arm,cortex-a15-gic + - oneOf: + - const: nvidia,tegra210-agic + - items: + - enum: + - nvidia,tegra186-agic + - nvidia,tegra194-agic + - const: nvidia,tegra210-agic + interrupt-controller: true "#address-cells": -- 2.7.4