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Subject: Re: [RFC PATCH 0/4] EDAC/ghes: Add EDAC device for recording the CPU
 error count
To:     Shiju Jose <shiju.jose@huawei.com>
Cc:     linux-edac@vger.kernel.org, linux-acpi@vger.kernel.org,
        linux-kernel@vger.kernel.org, bp@alien8.de, tony.luck@intel.com,
        rjw@rjwysocki.net, lenb@kernel.org, rrichter@marvell.com,
        linuxarm@huawei.com, jonathan.cameron@huawei.com
References: <20201105174233.1146-1-shiju.jose@huawei.com>
From:   James Morse <james.morse@arm.com>
Message-ID: <87b00978-8d5d-1917-b801-e6a36f704fb3@arm.com>
Date:   Fri, 6 Nov 2020 19:33:46 +0000
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Hi Shiju,

On 05/11/2020 17:42, Shiju Jose wrote:
> For the firmware-first error handling on ARM64 hardware platforms,
> CPU cache corrected error count is not recorded.
> Create an CPU EDAC device and device blocks for the CPU caches
> for this purpose. The EDAC device blocks  are created based on the
> CPU caches information represented in the ACPI PPTT.

Using the PPTT won't work on x86 systems. Can we use the core-code's common data to learn
about caches: struct cpu_cacheinfo and struct cacheinfo ?


Thanks,

James